Материал: 4HCT374A
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs
High±Performance Silicon±Gate CMOS
The MC54/74HCT374A may be used as a level converter for interfacing TTL or NMOS outputs to High±Speed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with the rising edge of Clock. The Output Enable does not affect the state of the flip±flops, but when Output Enable is high, the outputs are forced to the high±impedance state. Thus, data may be stored even when the outputs are not enabled.
The HCT374A is identical in function to the HCT574A, which has the input pins on the opposite side of the package from the output pins. This device is similar in function to the HCT534A, which has inverting outputs.
•Output Drive Capability: 15 LSTTL Loads
•TTL/NMOS±Compatible Input Levels
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 4.5 to 5.5 V
•Low Input Current: 1.0 μA
•In Compliance with the Requirements Defined by JEDEC Standard No. 7A
•Chip Complexity: 276 FETs or 69 Equivalent Gates
•Improvements over HCT374
ÐImproved Propagation Delays
Ð50% Lower Quiescent Power
ÐImproved Input Noise and Latchup Immunity
LOGIC DIAGRAM
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D0 |
3 |
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2 |
Q0 |
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D1 |
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Q1 |
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D2 |
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Q2 |
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DATA |
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D3 |
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Q3 |
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NONINVERTING |
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INPUTS |
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12 |
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D4 |
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Q4 |
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OUTPUTS |
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D5 |
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Q5 |
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D6 |
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Q6 |
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19 |
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D7 |
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Q7 |
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CLOCK |
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1 |
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PIN 20 = VCC |
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OUTPUT ENABLE |
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PIN 10 = GND |
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Design Criteria |
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Value |
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Units |
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Internal Gate Count* |
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69 |
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ea. |
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Internal Gate Propagation Delay |
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1.5 |
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ns |
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Internal Gate Power Dissipation |
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5.0 |
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μW |
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Speed Power Product |
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.0075 |
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pJ |
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* Equivalent to a two±input NAND gate.
MC54/74HCT374A
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J SUFFIX |
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20 |
CERAMIC PACKAGE |
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CASE 732±03 |
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1 |
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N SUFFIX |
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20 |
PLASTIC PACKAGE |
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CASE 738±03 |
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1 |
DW SUFFIX
20 |
SOIC PACKAGE |
1 |
CASE 751D±04 |
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20 |
SD SUFFIX |
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SSOP PACKAGE |
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1 |
CASE 940C±03 |
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20 |
DT SUFFIX |
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TSSOP PACKAGE |
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1 |
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CASE 948E±02 |
ORDERING INFORMATION
MC54HCTXXXAJ Ceramic
MC74HCTXXXAN Plastic
MC74HCTXXXADW SOIC
MC74HCTXXXASD SSOP
MC74HCTXXXADT TSSOP
PIN ASSIGNMENT
OUTPUT |
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1 |
20 |
VCC |
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ENABLE |
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Q0 |
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2 |
19 |
Q7 |
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D0 |
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3 |
18 |
D7 |
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D1 |
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4 |
17 |
D6 |
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Q1 |
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5 |
16 |
Q6 |
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Q2 |
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6 |
15 |
Q5 |
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D2 |
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7 |
14 |
D5 |
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D3 |
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8 |
13 |
D4 |
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Q3 |
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9 |
12 |
Q4 |
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GND |
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10 |
11 |
CLOCK |
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FUNCTION TABLE |
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Inputs |
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Output |
Output |
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Enable |
Clock |
D |
Q |
L |
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H |
H |
L |
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L |
L |
L |
L,H, |
X |
No Change |
H |
X |
X |
Z |
X = don't care |
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Z = high impedance |
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10/95
Motorola, Inc. 1995 |
REV 6 |
MC54/74HCT374A
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
± 1.5 to VCC + 1.5 |
V |
Vout |
DC Output Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
Iin |
DC Input Current, per Pin |
± 20 |
mA |
Iout |
DC Output Current, per Pin |
± 35 |
mA |
ICC |
DC Supply Current, VCC and GND Pins |
± 75 |
mA |
PD |
Power Dissipation in Still Air, Plastic or Ceramic DIP² |
750 |
mW |
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SOIC Package² |
500 |
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SSOP or TSSOP Package² |
450 |
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Tstg |
Storage Temperature |
± 65 to + 150 |
_C |
TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
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_C |
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(Plastic DIP, SOIC, SSOP or TSSOP Package) |
260 |
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(Ceramic DIP) |
300 |
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This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C
SOIC Package: ± 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
Min |
Max |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
4.5 |
5.5 |
V |
Vin, Vout |
DC Input Voltage, Output Voltage (Referenced to GND) |
0 |
VCC |
V |
TA |
Operating Temperature, All Package Types |
± 55 |
+ 125 |
_C |
tr, tf |
Input Rise and Fall Time (Figure 1) |
0 |
500 |
ns |
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit |
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VCC |
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± 55 to |
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Symbol |
Parameter |
Test Conditions |
V |
25_C |
v 85_C |
v 125_C |
Unit |
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VIH |
Minimum High±Level Input |
Vout = 0.1 V or VCC ± 0.1 V |
4.5 |
2.0 |
2.0 |
2.0 |
V |
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Voltage |
|Iout| v 20 μA |
5.5 |
2.0 |
2.0 |
2.0 |
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VIL |
Maximum Low±Level Input |
Vout = 0.1 V or VCC ± 0.1 V |
4.5 |
0.8 |
0.8 |
0.8 |
V |
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Voltage |
|Iout| v 20 μA |
5.5 |
0.8 |
0.8 |
0.8 |
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VOH |
Minimum High±Level Output |
Vin = VIH or VIL |
4.5 |
4.4 |
4.4 |
4.4 |
V |
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Voltage |
|Iout| v 20 μA |
5.5 |
5.4 |
5.4 |
5.4 |
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Vin = VIH or VIL |
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|Iout| v 6.0 mA |
4.5 |
3.98 |
3.84 |
3.7 |
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VOL |
Maximum Low±Level Output |
Vin = VIH or VIL |
4.5 |
0.1 |
0.1 |
0.1 |
V |
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Voltage |
|Iout| v 20 μA |
5.5 |
0.1 |
0.1 |
0.1 |
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Vin = VIH or VIL |
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|Iout| v 6.0 mA |
4.5 |
0.26 |
0.33 |
0.4 |
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Iin |
Maximum Input Leakage Current |
Vin = VCC or GND |
5.5 |
± 0.1 |
± 1.0 |
± 1.0 |
μA |
MOTOROLA |
2 |
MC54/74HCT374A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit |
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VCC |
± 55 to |
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Symbol |
Parameter |
Test Conditions |
V |
25_C |
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v 85_C |
v 125_C |
Unit |
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IOZ |
Maximum Three±State |
Output in High±Impedance State |
5.5 |
± 0.5 |
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± 5.0 |
± 10 |
μA |
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Leakage Current |
Vin = VIL or VIH |
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Vout = VCC or GND |
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ICC |
Maximum Quiescent Supply |
Vin = VCC or GND |
5.5 |
4.0 |
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40 |
160 |
μA |
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Current (per Package) |
Iout = 0 μA |
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ICC |
Additional Quiescent Supply |
Vin = 2.4 V, Any One Input |
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≥ ±55_C |
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25_C to 125_C |
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Current |
Vin = VCC or GND, Other Inputs |
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lout = 0 μA |
5.5 |
2.9 |
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2.4 |
mA |
NOTE: 1. Total Supply Current = ICC + ΣΔICC.
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
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Guaranteed Limit |
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± 55 to |
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Symbol |
Parameter |
25_C |
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v 85_C |
v 125_C |
Unit |
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fmax |
Maximum Clock Frequency (50% Duty Cycle) |
30 |
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24 |
20 |
MHz |
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(Figures 1 and 4) |
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tPLH, |
Maximum Propagation Delay, Clock to Q |
31 |
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39 |
47 |
ns |
tPHL |
(Figures 1 and 4) |
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tPLZ, |
Maximum Propagation Delay, Output Enable to Q |
30 |
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38 |
45 |
ns |
tPHZ |
(Figures 2 and 5) |
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tPZL, |
Maximum Propagation Delay, Output Enable to Q |
30 |
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38 |
45 |
ns |
tPZH |
(Figures 2 and 5) |
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tTLH, |
Maximum Output Transition Time, Any Output |
12 |
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15 |
18 |
ns |
tTHL |
(Figures 1 and 4) |
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Cin |
Maximum Input Capacitance |
10 |
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10 |
10 |
pF |
Cout |
Maximum Three±State Output Capacitance |
15 |
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15 |
15 |
pF |
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(Output in High±Impedance State) |
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NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).
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Typical @ 25°C, VCC = 5.0 V |
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CPD |
Power Dissipation Capacitance (Per Flip±Flop)* |
65 |
pF |
*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)
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Guaranteed Limit |
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± 55 to |
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Parameter |
25_C |
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v 85_C |
v 125_C |
Unit |
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tsu |
Minimum Setup Time, Data to Clock |
12 |
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15 |
18 |
ns |
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(Figure 3) |
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th |
Minimum Hold Time, Clock to Data |
5.0 |
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5.0 |
5.0 |
ns |
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tw |
Minimum Pulse Width, Clock |
12 |
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15 |
18 |
ns |
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(Figure 1) |
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tr, tf |
Maximum Input Rise and Fall Times |
500 |
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500 |
500 |
ns |
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(Figure 1) |
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3 |
MOTOROLA |
MC54/74HCT374A |
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SWITCHING WAVEFORMS |
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tr |
tf |
OUTPUT |
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3 V |
CLOCK |
2.7 V |
VCC |
1.3 V |
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ENABLE |
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GND |
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1.3 V |
GND |
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tPLZ |
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0.3 V |
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tPZL |
HIGH |
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tw |
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Q |
1.3 V |
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IMPEDANCE |
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1/fmax |
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10% |
VOL |
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tPLH |
tPHL |
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tPZH |
tPHZ |
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90% |
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90% |
VOH |
Q |
1.3 V |
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10% |
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1.3 V |
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HIGH |
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tTLH |
tTHL |
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IMPEDANCE |
Figure 1.
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VALID |
DATA |
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1.3 V |
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tsu |
th |
CLOCK |
1.3 V |
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Figure 3.
Figure 2.
3 V
GND
3 V
GND
TEST CIRCUITS
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TEST POINT |
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TEST POINT |
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OUTPUT |
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OUTPUT |
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1 kΩ |
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CONNECT TO VCC WHEN |
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DEVICE |
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DEVICE |
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TESTING tPLZ AND tPZL |
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CONNECT TO GND WHEN |
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UNDER |
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CL* |
UNDER |
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CL* |
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TESTING tPHZ AND tPZH |
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TEST |
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TEST |
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* Includes all probe and jig capacitance |
* Includes all probe and jig capacitance |
Figure 4. |
Figure 5. |
EXPANDED LOGIC DIAGRAM
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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3 |
4 |
7 |
8 |
13 |
14 |
17 |
18 |
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D Q |
D Q |
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D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
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C |
C |
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C |
C |
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CLOCK |
11 |
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OUTPUT |
1 |
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ENABLE |
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2 |
5 |
6 |
9 |
12 |
15 |
16 |
19 |
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Q0 |
Q1 |
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Q3 |
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Q6 |
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MOTOROLA |
4 |
MC54/74HCT374A
OUTLINE DIMENSIONS
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J SUFFIX |
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CERAMIC PACKAGE |
20 |
11 |
CASE 732±03 |
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ISSUE E |
1 |
10 |
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B |
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A |
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F |
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C |
L |
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N |
J |
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H |
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K |
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G |
M |
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D |
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SEATING |
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PLANE |
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NOTES:
1.LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION.
2.DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3.DIMENSIONS A AND B INCLUDE MENISCUS.
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MILLIMETERS |
INCHES |
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DIM |
MIN |
MAX |
MIN |
MAX |
A |
23.88 |
25.15 |
0.940 |
0.990 |
B |
6.60 |
7.49 |
0.260 |
0.295 |
C |
3.81 |
5.08 |
0.150 |
0.200 |
D |
0.38 |
0.56 |
0.015 |
0.022 |
F |
1.40 |
1.65 |
0.055 |
0.065 |
G |
2.54 BSC |
0.100 BSC |
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H |
0.51 |
1.27 |
0.020 |
0.050 |
J |
0.20 |
0.30 |
0.008 |
0.012 |
K |
3.18 |
4.06 |
0.125 |
0.160 |
L |
7.62 BSC |
0.300 BSC |
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M |
0 |
15 |
0 |
15 |
N |
0.25 |
1.02 |
0.010 |
0.040 |
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N SUFFIX |
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±A± |
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PLASTIC PACKAGE |
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CASE 738±03 |
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NOTES: |
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ISSUE E |
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1. DIMENSIONING AND TOLERANCING PER ANSI |
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20 |
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11 |
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Y14.5M, 1982. |
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B |
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2. CONTROLLING DIMENSION: INCH. |
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3. DIMENSION L TO CENTER OF LEAD WHEN |
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1 |
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10 |
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FORMED PARALLEL. |
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4. DIMENSION B DOES NOT INCLUDE MOLD |
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C |
L |
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FLASH. |
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INCHES |
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MILLIMETERS |
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DIM |
MIN |
MAX |
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MIN |
MAX |
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A |
1.010 |
1.070 |
25.66 |
27.17 |
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±T± |
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B |
0.240 |
0.260 |
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6.10 |
6.60 |
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K |
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C |
0.150 |
0.180 |
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3.81 |
4.57 |
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SEATING |
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D |
0.015 |
0.022 |
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0.39 |
0.55 |
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M |
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E |
0.050 BSC |
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1.27 BSC |
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PLANE |
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E |
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N |
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F |
0.050 |
0.070 |
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1.27 |
1.77 |
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G |
0.100 BSC |
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2.54 BSC |
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G |
F |
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J |
0.008 |
0.015 |
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0.21 |
0.38 |
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J 20 PL |
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K |
0.110 |
0.140 |
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2.80 |
3.55 |
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D 20 PL |
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0.25 (0.010) M |
T |
B |
M |
L |
0.300 BSC |
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7.62 BSC |
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M |
0 |
15 |
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0 |
15 |
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0.25 (0.010) M |
T |
A M |
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N |
0.020 |
0.040 |
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0.51 |
1.01 |
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DW SUFFIX |
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±A± |
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PLASTIC SOIC PACKAGE |
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NOTES: |
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CASE 751D±04 |
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1. DIMENSIONING AND TOLERANCING PER |
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ANSI Y14.5M, 1982. |
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20 |
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11 |
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ISSUE E |
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2. CONTROLLING DIMENSION: MILLIMETER. |
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3. DIMENSIONS A AND B DO NOT INCLUDE |
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MOLD PROTRUSION. |
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±B± |
10X P |
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4. MAXIMUM MOLD PROTRUSION 0.150 |
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(0.006) PER SIDE. |
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0.010 (0.25) M |
B M |
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5. DIMENSION D DOES NOT INCLUDE |
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DAMBAR PROTRUSION. ALLOWABLE |
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1 |
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10 |
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DAMBAR PROTRUSION SHALL BE 0.13 |
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(0.005) TOTAL IN EXCESS OF D DIMENSION |
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AT MAXIMUM MATERIAL CONDITION. |
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20X D |
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J |
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MILLIMETERS |
INCHES |
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0.010 (0.25) M |
T |
A |
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B |
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DIM |
MIN |
MAX |
MIN |
MAX |
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S |
S |
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A |
12.65 |
12.95 |
0.499 |
0.510 |
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B |
7.40 |
7.60 |
0.292 |
0.299 |
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F |
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C |
2.35 |
2.65 |
0.093 |
0.104 |
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D |
0.35 |
0.49 |
0.014 |
0.019 |
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F |
0.50 |
0.90 |
0.020 |
0.035 |
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R X 45 |
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G |
1.27 BSC |
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0.050 BSC |
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J |
0.25 |
0.32 |
0.010 |
0.012 |
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K |
0.10 |
0.25 |
0.004 |
0.009 |
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M |
0 |
7 |
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0 |
7 |
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C |
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P |
10.05 |
10.55 |
0.395 |
0.415 |
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R |
0.25 |
0.75 |
0.010 |
0.029 |
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±T± |
SEATING |
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PLANE |
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M |
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18X G |
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K |
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5 |
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MOTOROLA |