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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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8-Bit Addressable Latch

1-of-8 Decoder

High±Performance Silicon±Gate CMOS

The MC54/74HC259A is identical in pinout to the LS259. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

The HC259A has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all non±addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one±of±eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode all outputs are LOW and unaffected by the address and data inputs. When operating the HC259A as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 μA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard No. 7A

•Chip Complexity: 202 FETs or 50.5 Equivalent Gates

LOGIC DIAGRAM

ADDRESS	A0	1	4	Q0
ADDRESS	A1	2	5	Q1
INPUTS	A1	2	5	Q1
INPUTS	A2	3	6	Q2
	A2	3	6	Q2
			7	Q3	NONINVERTING
			9	Q4	OUTPUTS
DATA IN		13	10 Q5
			11	Q6
			12	Q7
RESET		15	PIN 16 = V
		14			CC
ENABLE		14	PIN 8 = GND

MC54/74HC259A

		J SUFFIX
16	CERAMIC PACKAGE
16		CASE 620±10
	1
		N SUFFIX
16	PLASTIC PACKAGE
16		CASE 648±08
		CASE 648±08
	1
		D SUFFIX
16		SOIC PACKAGE
	1	CASE 751B±05
		DT SUFFIX
16		TSSOP PACKAGE
	1	CASE 948F±01
	ORDERING INFORMATION
	MC54HCXXXAJ	Ceramic
	MC74HCXXXAN	Plastic
	MC74HCXXXAD	SOIC

MC74HCXXXADT TSSOP

PIN ASSIGNMENT

A0	1	16	VCC


A1	2	15	RESET
A2	3	14	ENABLE

Q0	4	13	DATA IN

Q1	5	12	Q7

Q2	6	11	Q6

Q3	7	10	Q5


GND	8	9	Q4

MODE SELECTION TABLE

Enable	Reset	Mode

L	H	Addressable Latch
H	H	Memory
L	L	8±Line Demultiplexer
H	L	Reset

LATCH SELECTION TABLE

Address Inputs			Latch
C	B	A	Addressed

L	L	L	Q0
L	L	H	Q1
L	H	L	Q2
L	H	H	Q3
H	L	L	Q4
H	L	H	Q5
H	H	L	Q6
H	H	H	Q7

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10/95

Motorola, Inc. 1995

REV 0

MC54/74HC259A

MAXIMUM RATINGS*

Symbol	Parameter	Value	Unit

VCC	DC Supply Voltage (Referenced to GND)	± 0.5 to + 7.0	V
Vin	DC Input Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
Vout	DC Output Voltage (Referenced to GND)	± 0.5 to VCC + 0.5	V
Iin	DC Input Current, per Pin	± 20	mA
Iout	DC Output Current, per Pin	± 25	mA
ICC	DC Supply Current, VCC and GND Pins	± 50	mA
ICC	DC Supply Current, VCC and GND Pins	± 50	mA
PD	Power Dissipation in Still Air, Plastic or Ceramic DIP²	750	mW
	SOIC Package²	500
	TSSOP Package²	450

Tstg	Storage Temperature	± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds		_C
	Plastic DIP, SOIC or TSSOP Package	260
	(Ceramic DIP)	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C

SOIC Package: ± 7 mW/_C from 65_ to 125_C

TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit

VCC	DC Supply Voltage (Referenced to GND)		2.0	6.0	V
Vin, Vout	DC Input Voltage, Output Voltage (Referenced to GND)		0	VCC	V
TA	Operating Temperature, All Package Types		± 55	+ 125	_C
tr, tf	Input Rise and Fall Time	VCC = 2.0 V	0	1000	ns
	(Figure 1)	VCC = 3.0 V	0	600
		VCC = 4.5 V	0	500
		VCC = 6.0 V	0	400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit

VIH	Minimum High±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	1.5	1.5	1.5	V
	Voltage	\|Iout\| v 20 μA	3.0	2.1	2.1	2.1
			4.5	3.15	3.15	3.15
			6.0	4.2	4.2	4.2

VIL	Maximum Low±Level Input	Vout = 0.1 V or VCC ± 0.1 V	2.0	0.5	0.5	0.5	V
	Voltage	\|Iout\| v 20 μA	3.0	0.9	0.9	0.9
			4.5	1.35	1.35	1.35
			6.0	1.80	1.80	1.80

VOH	Minimum High±Level Output	Vin = VIH or VIL	2.0	1.9	1.9	1.9	V
	Voltage	\|Iout\| v 20 μA	4.5	4.4	4.4	4.4
			6.0	5.9	5.9	5.9

		Vin = VIH or VIL \|Iout\| v 2.4 mA	3.0	2.48	2.34	2.20
		\|Iout\| v 4.0 mA	4.5	3.98	3.84	3.70
		\|Iout\| v 5.2 mA	6.0	5.48	5.34	5.20

MOTOROLA

MC54/74HC259A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

				Guaranteed Limit

			VCC	± 55 to
Symbol	Parameter	Test Conditions	V	25_C	v 85_C	v 125_C	Unit

VOL	Maximum Low±Level Output	Vin = VIH or VIL	2.0	0.1	0.1	0.1	V
	Voltage	\|Iout\| v 20 μA	4.5	0.1	0.1	0.1
			6.0	0.1	0.1	0.1

		Vin = VIH or VIL \|Iout\| v 2.4 mA	3.0	0.26	0.33	0.40
		\|Iout\| v 4.0 mA	4.5	0.26	0.33	0.40
		\|Iout\| v 5.2 mA	6.0	0.26	0.33	0.40
Iin	Maximum Input Leakage Current	Vin = VCC or GND	6.0	± 0.1	± 1.0	± 1.0	μA
ICC	Maximum Quiescent Supply	Vin = VCC or GND	6.0	4	40	160	μA
	Current (per Package)	Iout = 0 μA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
		VCC	± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit

tPLH,	Maximum Propagation Delay, Data to Output	2.0	125	160	175	ns
tPHL	(Figures 1 and 6)	3.0	45	60	70
		4.5	32	32	42
		6.0	25	28	33

tPLH,	Maximum Propagation Delay, Address Select to Output	2.0	150	175	200	ns
tPHL	(Figures 2 and 6)	3.0	60	70	80
		4.5	32	40	45
		6.0	28	30	35

tPLH,	Maximum Propagation Delay, Enable to Output	2.0	150	175	200	ns
tPHL	(Figures 3 and 6)	3.0	60	70	80
		4.5	32	40	45
		6.0	28	30	35

tPHL	Maximum Propagation Delay, Reset to Output	2.0	110	125	160	ns
	(Figures 4 and 6)	3.0	36	45	60
		4.5	22	26	32
		6.0	19	23	28

tTLH,	Maximum Output Transition Time, Any Output	2.0	75	95	110	ns
tTHL	(Figures 1 and 6)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	16	19

Cin	Maximum Input Capacitance	Ð	10	10	10	pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

			Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Package)*			30		pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

MC54/74HC259A

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

			Guaranteed Limit
		VCC
		VCC	± 55 to
Symbol	Parameter	V	25_C	v 85_C	v 125_C	Unit

tsu	Minimum Setup Time, Address or Data to Enable	2.0	75	95	110	ns
	(Figure 5)	3.0	30	40	55
		4.5	15	19	22
		6.0	13	16	19

th	Minimum Hold Time, Enable to Address or Data	2.0	1	1	1	ns
	(Figure 5)	3.0	1	1	1
		4.5	1	1	1
		6.0	1	1	1

tw	Minimum Pulse Width, Reset or Enable	2.0	70	90	100	ns
	(Figure 3 or 4)	3.0	27	32	36
		4.5	15	19	22
		6.0	13	16	19

tr, tf	Maximum Input Rise and Fall Times	2.0	1000	1000	1000	ns
	(Figure 1)	3.0	800	800	800
		4.5	500	500	500
		6.0	400	400	400

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

MOTOROLA

MC54/74HC259A

SWITCHING WAVEFORMS

			DATA IN	VCC
			DATA IN
				GND
				VCC
				50%
tr	tf	VCC	ADDRESS	GND
DATA IN			ADDRESS
DATA IN	90%		SELECT	VCC
	50%			VCC
	10%	GND		50%
tPLH		tPHL		GND
	90%		tPHL	tPLH
OUTPUT Q	50%
OUTPUT Q	10%		OUTPUT Q	50%
	tTLH	tTHL	OUTPUT Q	50%
	tTLH	tTHL
	Figure 1.			Figure 2.

				VCC		VCC
DATA IN						VCC
DATA IN					DATA IN
				GND	DATA IN	GND
	tw	tw		GND

						tw
				VCC		tw
				VCC		V
ENABLE	50%	50%	50%			CC
ENABLE	50%	50%	50%	GND	RESET	50%
	tPHL		tPLH	GND		GND
	tPHL		tPLH			tPHL
						tPHL
OUTPUT Q					OUTPUT Q	50%

	Figure 3.				Figure 4.
					TEST POINT
DATA IN			VCC		OUTPUT
DATA IN			VCC	DEVICE
OR	50%			DEVICE
ADDRESS			GND	UNDER	CL*
SELECT	th(H)	tsu	th(L)	TEST	CL*
	tsu	tsu	VCC
ENABLE	50%		VCC
ENABLE	50%
			GND
				* Includes all probe and jig capacitance
	Figure 5.			Figure 6. Test Circuit

MOTOROLA

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