Материал: 74HC32A
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input OR Gate
High±Performance Silicon±Gate CMOS
The MC54/74HC32A is identical in pinout to the LS32. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
•Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS and TTL
•Operating Voltage Range: 2 to 6V
•Low Input Current: 1μA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance With the JEDEC Standard No. 7A Requirements
•Chip Complexity: 48 FETs or 12 Equivalent Gates
LOGIC DIAGRAM
A1 |
1 |
3 |
Y1 |
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2 |
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B1 |
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A2 |
4 |
6 |
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Y2 |
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B2 |
5 |
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9 |
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Y = A+B |
A3 |
8 |
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Y3 |
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B3 |
10 |
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A4 |
12 |
11 |
Y4 |
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13 |
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B4 |
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PIN 14 = VCC
PIN 7 = GND
Pinout: 14±Lead Packages (Top View)
VCC |
B4 |
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A4 |
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Y4 |
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B3 |
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A3 |
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Y3 |
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14 |
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13 |
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12 |
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11 |
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10 |
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9 |
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8 |
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MC54/74HC32A
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J SUFFIX |
CERAMIC PACKAGE |
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14 |
CASE 632±08 |
1 |
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N SUFFIX |
PLASTIC PACKAGE |
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14 |
CASE 646±06 |
1 |
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D SUFFIX |
14 |
SOIC PACKAGE |
1 |
CASE 751A±03 |
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DT SUFFIX |
14 |
TSSOP PACKAGE |
1 |
CASE 948B±03 |
ORDERING INFORMATION |
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MC54HCXXAJ |
Ceramic |
MC74HCXXAN |
Plastic |
MC74HCXXAD |
SOIC |
MC74HCXXADT TSSOP |
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FUNCTION TABLE
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Inputs |
Output |
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A |
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B |
Y |
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L |
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L |
L |
L |
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H |
H |
H |
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L |
H |
H |
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H |
H |
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1 |
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2 |
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3 |
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4 |
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5 |
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6 |
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7 |
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A1 |
B1 |
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Y1 |
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A2 |
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B2 |
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Y2 |
GND |
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10/95
Motorola, Inc. 1995 |
REV 6 |
MC54/74HC32A
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
Vout |
DC Output Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
Iin |
DC Input Current, per Pin |
± 20 |
mA |
Iout |
DC Output Current, per Pin |
± 25 |
mA |
ICC |
DC Supply Current, VCC and GND Pins |
± 50 |
mA |
PD |
Power Dissipation in Still Air, Plastic or Ceramic DIP² |
750 |
mW |
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SOIC Package² |
500 |
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TSSOP Package² |
450 |
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Tstg |
Storage Temperature |
± 65 to + 150 |
_C |
TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
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_C |
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Plastic DIP, SOIC or TSSOP Package |
260 |
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Ceramic DIP |
300 |
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This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C
Ceramic DIP: ± 10 mW/_C from 100_ to 125_C
SOIC Package: ± 7 mW/_C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Max |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
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2.0 |
6.0 |
V |
Vin, Vout |
DC Input Voltage, Output Voltage (Referenced to GND) |
0 |
VCC |
V |
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TA |
Operating Temperature, All Package Types |
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± 55 |
+ 125 |
_C |
tr, tf |
Input Rise and Fall Time |
VCC = 2.0 V |
0 |
1000 |
ns |
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(Figure 1) |
VCC = 4.5 V |
0 |
500 |
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VCC = 6.0 V |
0 |
400 |
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MOTOROLA |
3±2 |
MC54/74HC32A
DC CHARACTERISTICS (Voltages Referenced to GND)
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VCC |
Guaranteed Limit |
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Symbol |
Parameter |
Condition |
V |
±55 to 25°C |
≤85°C |
≤125°C |
Unit |
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VIH |
Minimum High±Level Input Voltage |
Vout = 0.1V or VCC ±0.1V |
2.0 |
1.50 |
1.50 |
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1.50 |
V |
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|Iout| ≤ 20μA |
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3.0 |
2.10 |
2.10 |
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2.10 |
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4.5 |
3.15 |
3.15 |
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3.15 |
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6.0 |
4.20 |
4.20 |
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4.20 |
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VIL |
Maximum Low±Level Input Voltage |
Vout = 0.1V or VCC ± 0.1V |
2.0 |
0.50 |
0.50 |
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0.50 |
V |
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|Iout| ≤ 20μA |
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3.0 |
0.90 |
0.90 |
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0.90 |
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4.5 |
1.35 |
1.35 |
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1.35 |
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6.0 |
1.80 |
1.80 |
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1.80 |
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VOH |
Minimum High±Level Output |
Vin = VIH or VIL |
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2.0 |
1.9 |
1.9 |
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1.9 |
V |
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Voltage |
|Iout| ≤ 20μA |
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4.5 |
4.4 |
4.4 |
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4.4 |
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6.0 |
5.9 |
5.9 |
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5.9 |
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Vin =VIH or VIL |
|Iout| ≤ 2.4mA |
3.0 |
2.48 |
2.34 |
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2.20 |
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|Iout| ≤ 4.0mA |
4.5 |
3.98 |
3.84 |
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3.70 |
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|Iout| ≤ 5.2mA |
6.0 |
5.48 |
5.34 |
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5.20 |
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VOL |
Maximum Low±Level Output |
Vin = VIH or VIL |
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2.0 |
0.1 |
0.1 |
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0.1 |
V |
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Voltage |
|Iout| ≤ 20μA |
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4.5 |
0.1 |
0.1 |
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0.1 |
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6.0 |
0.1 |
0.1 |
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0.1 |
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Vin = VIH or VIL |
|Iout| ≤ 2.4mA |
3.0 |
0.26 |
0.33 |
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0.40 |
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|Iout| ≤ 4.0mA |
4.5 |
0.26 |
0.33 |
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0.40 |
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|Iout| ≤ 5.2mA |
6.0 |
0.26 |
0.33 |
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0.40 |
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Iin |
Maximum Input Leakage Current |
Vin = VCC or GND |
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6.0 |
±0.1 |
±1.0 |
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±1.0 |
μA |
ICC |
Maximum Quiescent Supply |
Vin = VCC or GND |
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6.0 |
1.0 |
10 |
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40 |
μA |
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Current (per Package) |
Iout = 0μA |
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
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VCC |
Guaranteed Limit |
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Symbol |
Parameter |
V |
±55 to 25°C |
≤85°C |
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≤125°C |
Unit |
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tPLH, |
Maximum Propagation Delay, Input A or B to Output Y |
2.0 |
75 |
95 |
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110 |
ns |
tPHL |
(Figures 1 and 2) |
3.0 |
30 |
40 |
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55 |
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4.5 |
15 |
19 |
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22 |
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6.0 |
13 |
16 |
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19 |
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tTLH, |
Maximum Output Transition Time, Any Output |
2.0 |
75 |
95 |
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110 |
ns |
tTHL |
(Figures 1 and 2) |
3.0 |
27 |
32 |
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36 |
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4.5 |
15 |
19 |
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22 |
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6.0 |
13 |
16 |
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19 |
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Cin |
Maximum Input Capacitance |
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10 |
10 |
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10 |
pF |
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).
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Typical @ 25°C, VCC = 5.0 V, VEE = 0 V |
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CPD |
Power Dissipation Capacitance (Per Buffer)* |
20 |
pF |
*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
3±3 |
MOTOROLA |
MC54/74HC32A
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tr |
tf |
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90% |
VCC |
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INPUT |
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50% |
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A OR B |
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10% |
GND |
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tPLH |
tPHL |
90%
OUTPUT Y 50%
10%
tTLH |
tTHL |
Figure 1. Switching Waveforms
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TEST |
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POINT |
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OUTPUT |
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DEVICE |
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UNDER |
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CL* |
TEST |
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*Includes all probe and jig capacitance
Figure 2. Test Circuit
A
Y
B
Figure 3. Expanded Logic Diagram
(1/4 of the Device)
MOTOROLA |
3±4 |
MC54/74HC32A
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC DIP PACKAGE
CASE 632±08
ISSUE Y
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-A- |
14 |
8 |
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-B- |
1 |
7 |
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C |
-T- |
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K |
SEATING |
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PLANE |
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F |
G |
N |
D 14 PL
0.25 (0.010) M T A S
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NOTES: |
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1. DIMENSIONING AND TOLERANCING PER ANSI |
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Y14.5M, 1982. |
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2. CONTROLLING DIMENSION: INCH. |
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3. DIMENSION L TO CENTER OF LEAD WHEN |
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FORMED PARALLEL. |
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4. DIMESNION F MAY NARROW TO 0.76 (0.030) |
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L |
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WHERE THE LEAD ENTERS THE CERAMIC |
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BODY. |
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INCHES |
MILLIMETERS |
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DIM |
MIN |
MAX |
MIN |
MAX |
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A |
0.750 |
0.785 |
19.05 |
19.94 |
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B |
0.245 |
0.280 |
6.23 |
7.11 |
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C |
0.155 |
0.200 |
3.94 |
5.08 |
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D |
0.015 |
0.020 |
0.39 |
0.50 |
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F |
0.055 |
0.065 |
1.40 |
1.65 |
M |
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G |
0.100 BSC |
2.54 BSC |
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J |
0.008 |
0.015 |
0.21 |
0.38 |
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J 14 PL |
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K |
0.125 |
0.170 |
3.18 |
4.31 |
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L |
0.300 BSC |
7.62 BSC |
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0.25 (0.010) |
M |
T |
B |
S |
M |
0° |
15° |
0° |
15° |
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N |
0.020 |
0.040 |
0.51 |
1.01 |
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646±06
ISSUE L
14 |
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8 |
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B |
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1 |
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7 |
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A |
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F |
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L |
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C |
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N |
J |
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SEATING |
K |
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H |
G |
D |
PLANE |
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M |
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NOTES:
1.LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.
2.DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4.ROUNDED CORNERS OPTIONAL.
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INCHES |
MILLIMETERS |
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DIM |
MIN |
MAX |
MIN |
MAX |
A |
0.715 |
0.770 |
18.16 |
19.56 |
B |
0.240 |
0.260 |
6.10 |
6.60 |
C |
0.145 |
0.185 |
3.69 |
4.69 |
D |
0.015 |
0.021 |
0.38 |
0.53 |
F |
0.040 |
0.070 |
1.02 |
1.78 |
G |
0.100 BSC |
2.54 BSC |
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H |
0.052 |
0.095 |
1.32 |
2.41 |
J |
0.008 |
0.015 |
0.20 |
0.38 |
K |
0.115 |
0.135 |
2.92 |
3.43 |
L |
0.300 BSC |
7.62 BSC |
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M |
0 |
10 |
0 |
10 |
N |
0.015 |
0.039 |
0.39 |
1.01 |
3±5 |
MOTOROLA |