Philips Semiconductors Product specification
PowerMOS transistor |
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BUK102-50GL |
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Logic level TOPFET |
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DESCRIPTION |
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QUICK REFERENCE DATA |
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Monolithic temperature and |
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PARAMETER |
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MAX. |
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UNIT |
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overload protected logic level power |
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MOSFET in a 3 pin plastic |
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VDS |
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Continuous drain source voltage |
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50 |
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envelope, intended as a general |
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ID |
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Continuous drain current |
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45 |
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A |
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purpose switch for automotive |
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PD |
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Total power dissipation |
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125 |
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systems and other applications. |
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Tj |
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Continuous junction temperature |
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150 |
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˚C |
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APPLICATIONS |
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RDS(ON) |
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Drain-source on-state resistance |
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mΩ |
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VIS = 5 V |
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General controller for driving |
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lamps |
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motors |
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solenoids |
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heaters |
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FEATURES |
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FUNCTIONAL BLOCK DIAGRAM |
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Vertical power DMOS output |
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stage |
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DRAIN |
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Low on-state resistance |
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Overload protection against |
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over temperature |
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Overload protection against |
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O/V |
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short circuit load |
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CLAMP |
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Latched overload protection |
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POWER |
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reset by input |
INPUT |
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MOSFET |
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5 V input level |
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RIG |
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Low threshold voltage |
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also allows 5 V control |
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Control of power MOSFET |
LOGIC AND |
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and supply of overload |
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PROTECTION |
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protection circuits |
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derived from input |
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ESD protection on input pin |
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Overvoltage clamping for turn |
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off of inductive loads |
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SOURCE |
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Fig.1. Elements of the TOPFET. |
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PINNING - TO220AB |
PIN CONFIGURATION |
SYMBOL |
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PIN |
DESCRIPTION |
tab |
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D |
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TOPFET |
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1 |
input |
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2 |
drain |
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I |
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P |
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3 |
source |
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tab |
drain |
1 2 3 |
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January 1993 |
1 |
Rev 1.200 |
Philips Semiconductors Product specification
PowerMOS transistor |
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BUK102-50GL |
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Logic level TOPFET |
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LIMITING VALUES |
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Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) |
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SYMBOL |
PARAMETER |
CONDITIONS |
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MIN. |
MAX. |
UNIT |
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VDSS |
Continuous off-state drain source |
VIS = 0 V |
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50 |
V |
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voltage1 |
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VIS |
Continuous input voltage |
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≤ 25 ˚C; VIS = 5 V |
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0 |
6 |
V |
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ID |
Continuous drain current |
Tmb |
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45 |
A |
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ID |
Continuous drain current |
Tmb |
≤ 100 ˚C; VIS = 5 V |
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28 |
A |
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IDRM |
Repetitive peak on-state drain current |
Tmb |
≤ 25 ˚C; VIS = 5 V |
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180 |
A |
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PD |
Total power dissipation |
Tmb |
≤ 25 ˚C |
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125 |
W |
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Tstg |
Storage temperature |
- |
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-55 |
150 |
˚C |
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T |
Continuous junction temperature2 |
normal operation |
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150 |
˚C |
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j |
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Tsold |
Lead temperature |
during soldering |
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250 |
˚C |
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OVERLOAD PROTECTION LIMITING VALUES
With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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V |
Protection supply voltage3 |
for valid protection |
4 |
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V |
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ISP |
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Over temperature protection |
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VDDP(T) |
Protected drain source supply voltage |
VIS = 5 |
V |
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50 |
V |
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Short circuit load protection |
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V |
Protected drain source supply voltage4 |
V = 5 |
V |
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24 |
V |
DDP(P) |
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IS |
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PDSM |
Instantaneous overload dissipation |
Tmb = 25 ˚C |
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2.1 |
kW |
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OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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IDROM |
Repetitive peak clamping current |
VIS = 0 V |
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45 |
A |
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EDSM |
Non-repetitive clamping energy |
Tmb |
≤ 25 ˚C; IDM = 25 A; |
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1 |
J |
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VDD |
≤ 25 V; inductive load |
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EDRM |
Repetitive clamping energy |
Tmb |
≤ 85 ˚C; IDM = 16 A; |
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80 |
mJ |
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VDD |
≤ 20 V; f = 250 Hz |
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ESD LIMITING VALUE
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VC |
Electrostatic discharge capacitor |
Human body model; |
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2 |
kV |
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voltage |
C = 250 pF; R = 1.5 kΩ |
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1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 The input voltage for which the overload protection circuits are functional.
4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum. For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
January 1993 |
2 |
Rev 1.200 |
Philips Semiconductors Product specification
PowerMOS transistor |
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BUK102-50GL |
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Logic level TOPFET |
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THERMAL CHARACTERISTICS |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Thermal resistance |
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Rth j-mb |
Junction to mounting base |
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0.8 |
1.0 |
K/W |
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Rth j-a |
Junction to ambient |
in free air |
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60 |
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K/W |
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STATIC CHARACTERISTICS |
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Tmb = 25 ˚C unless otherwise specified |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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V(CL)DSS |
Drain-source clamping voltage |
VIS = 0 V; ID = 10 mA |
50 |
- |
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V |
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V(CL)DSS |
Drain-source clamping voltage |
VIS = 0 V; IDM = 2 A; tp £ 300 ms; |
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70 |
V |
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d £ 0.01 |
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mA |
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IDSS |
Zero input voltage drain current |
VDS = 12 V; VIS = 0 V |
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0.5 |
10 |
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IDSS |
Zero input voltage drain current |
VDS = 50 V; VIS = 0 V |
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1 |
20 |
mA |
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IDSS |
Zero input voltage drain current |
VDS = 40 V; VIS = 0 V; Tj = 125 ˚C |
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10 |
100 |
mA |
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RDS(ON) |
Drain-source on-state |
IDM = 25 A; VIS = 5 V |
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30 |
35 |
mW |
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resistance |
tp £ 300 ms; d £ 0.01 |
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OVERLOAD PROTECTION CHARACTERISTICS
TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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EDS(TO) |
Short circuit load protection1 |
Tmb = 25 ˚C; L £ 10 mH |
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Overload threshold energy |
VDD = 13 V; VIS = 5 V |
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1.1 |
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J |
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td sc |
Response time |
VDD = 13 V; VIS = 5 V |
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0.8 |
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ms |
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Over temperature protection |
VIS = 5 V; from ID ³ 2 A2 |
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Tj(TO) |
Threshold junction temperature |
150 |
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˚C |
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VIS(TO) |
Input threshold voltage |
VDS = 5 V; ID = 1 mA |
1.0 |
1.5 |
2.0 |
V |
IIS |
Input supply current |
VIS = 5 V; normal operation |
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0.2 |
0.35 |
mA |
V |
Protection reset voltage3 |
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2.0 |
2.6 |
3.5 |
V |
ISR |
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VISR |
Protection reset voltage |
Tj = 150 ˚C |
1.0 |
- |
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IISL |
Input supply current |
VIS = 5 V; protection latched |
2 |
3.8 |
10 |
mA |
V(BR)IS |
Input clamp voltage |
II = 10 mA |
6 |
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V |
RIG |
Input series resistance |
to gate of power MOSFET |
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1.5 |
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kW |
1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDSP maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES.
2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID ensures this condition.
3 The input voltage below which the overload protection circuits will be reset.
January 1993 |
3 |
Rev 1.200 |
Philips Semiconductors Product specification
PowerMOS transistor |
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BUK102-50GL |
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Logic level TOPFET |
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TRANSFER CHARACTERISTICS |
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Tmb = 25 ˚C |
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PARAMETER |
CONDITIONS |
MIN. |
TYP. |
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UNIT |
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gfs |
Forward transconductance |
VDS = 10 V; IDM = 25 A tp ≤ 300 μs; |
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28 |
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δ ≤ |
0.01 |
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I |
Drain current1 |
V |
= 13 V; V = 5 V |
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60 |
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A |
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D(SC) |
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DS |
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IS |
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SWITCHING CHARACTERISTICS |
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Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figures and test circuits. |
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SYMBOL |
PARAMETER |
CONDITIONS |
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td on |
Turn-on delay time |
VDD = 13 V; VIS = 5 V |
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2 |
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tr |
Rise time |
resistive load RL = 1.1 Ω |
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8 |
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td off |
Turn-off delay time |
VDD = 13 V; VIS = 0 V |
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8 |
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tf |
Fall time |
resistive load RL = 1.1 Ω |
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8 |
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td on |
Turn-on delay time |
VDD = 13 V; VIS = 5 V |
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3.7 |
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tr |
Rise time |
inductive load IDM = 11 A |
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3.7 |
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td off |
Turn-off delay time |
VDD = 13 V; VIS = 0 V |
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13 |
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tf |
Fall time |
inductive load IDM = 11 A |
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1.4 |
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REVERSE DIODE LIMITING VALUE |
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PARAMETER |
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CONDITIONS |
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IS |
Continuous forward current |
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Tmb ≤ 25 ˚C; VIS = 0 V |
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A |
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REVERSE DIODE CHARACTERISTICS |
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Tmb = 25 ˚C |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
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VSDS |
Forward voltage |
IS = 50 A; VIS = 0 V; tp = 300 μs |
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1.0 |
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1.5 |
V |
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t |
Reverse recovery time |
not applicable2 |
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rr |
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ENVELOPE CHARACTERISTICS |
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SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
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Ld |
Internal drain inductance |
Measured from contact screw on |
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3.5 |
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nH |
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tab to centre of die |
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Ld |
Internal drain inductance |
Measured from drain lead 6 mm |
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4.5 |
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nH |
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from package to centre of die |
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Ls |
Internal source inductance |
Measured from source lead 6 mm |
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7.5 |
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nH |
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from package to source bond pad |
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1 During overload before short circuit load protection operates.
2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
January 1993 |
4 |
Rev 1.200 |
Philips Semiconductors |
Product specification |
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PowerMOS transistor |
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BUK102-50GL |
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Logic level TOPFET |
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120 |
PD% |
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Normalised Power Derating |
Zth / (K/W) |
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BUK102-50GL |
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10 |
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110 |
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100 |
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90 |
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1 |
D = |
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80 |
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0.5 |
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70 |
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0.2 |
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60 |
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0.1 |
0.1 |
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50 |
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0.05 |
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40 |
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0.02 |
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30 |
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0.01 |
0 |
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P |
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tp |
D = |
tp |
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20 |
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D |
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T |
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10 |
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T |
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t |
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0 |
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0.001 |
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0 |
20 |
40 |
60 |
80 |
100 |
120 |
140 |
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1E-07 |
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1E-05 |
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1E-03 |
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1E-01 |
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1E+01 |
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Tmb / |
C |
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t / s |
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Fig.2. |
Normalised limiting power dissipation. |
Fig.5. |
Transient thermal impedance. |
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PD% = 100×PD/PD(25 ˚C) = f(Tmb) |
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Zth j-mb = f(t); parameter D = tp/T |
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120 |
ID% |
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Normalised Current Derating |
ID / A |
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BUK102-50GL |
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120 |
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110 |
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110 |
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VIS / V = |
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100 |
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100 |
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90 |
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90 |
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6.0 |
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80 |
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80 |
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5.5 |
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70 |
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70 |
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5.0 |
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60 |
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60 |
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4.5 |
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50 |
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50 |
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4.0 |
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40 |
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40 |
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3.5 |
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30 |
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30 |
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20 |
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20 |
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3.0 |
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10 |
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10 |
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2.5 |
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120 |
140 |
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4 |
6 |
8 |
10 |
12 |
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14 |
16 |
18 |
20 |
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Tmb / |
C |
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VDS / V |
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Fig.3. |
Normalised continuous drain current. |
Fig.6. |
Typical output characteristics, Tj |
= 25 ˚C. |
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ID% = 100×ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V |
ID = f(VDS); parameter VIS; tp = 250 ms |
& tp < td sc |
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1000 |
ID & IDM / A |
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BUK102-50GL |
ID / A |
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BUK102-50GL |
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100 |
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Overload protection characteristics not shown |
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90 |
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VIS / V = |
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tp = |
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80 |
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5.0 |
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VDS/ID |
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70 |
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100 |
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= |
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10 us |
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4.5 |
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RDS(ON) |
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60 |
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100 us |
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50 |
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4.0 |
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1 ms |
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40 |
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3.5 |
10 |
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DC |
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30 |
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10 ms |
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20 |
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3.0 |
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100 ms |
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10 |
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2.5 |
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1 |
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0 |
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1 |
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3 |
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5 |
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1 |
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10 |
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100 |
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0 |
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2 |
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4 |
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VDS / V |
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VDS / V |
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Fig.4. Safe operating area. Tmb = 25 ˚C |
Fig.7. Typical on-state characteristics, Tj = 25 ˚C. |
ID & IDM = f(VDS); IDM single pulse; parameter tp |
ID = f(VDS); parameter VIS; tp = 250 ms |
January 1993 |
5 |
Rev 1.200 |