Материал: 9015
Philips Semiconductors |
Product specification |
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PowerMOS transistor |
BUK102-50GL |
Logic level TOPFET |
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100 |
RDS(ON) / mOhm |
BUK102-50GL |
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VIS / V = |
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3.5 |
4 |
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4.5 |
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50 |
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5 |
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0 |
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0 |
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20 |
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80 |
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ID / A |
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Fig.8. |
Typical on-state resistance, Tj |
= 25 ˚C. |
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RDS(ON) = f(ID); parameter VIS; tp = 250 ms |
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ID / A |
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BUK102-50GL |
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100 |
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80 |
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60 |
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40 |
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20 |
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0 |
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VIS / V |
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Fig.9. |
Typical transfer characteristics, Tj = 25 ˚C. |
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ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 ms |
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30 |
gfs / S |
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BUK102-50GL |
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20 |
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10 |
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0 |
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0 |
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50 |
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100 |
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ID / A |
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Fig.10. |
Typical transconductance, Tj |
= 25 ˚C. |
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gfs = f(ID); conditions: VDS = 10 V; tp = 250 ms |
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a |
Normalised RDS(ON) = f(Tj) |
1.5 |
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1.0 |
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0.5 |
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-60 |
-40 -20 |
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80 100 120 140 |
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Tj / |
C |
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Fig.11. Normalised drain-source on-state resistance. |
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a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VIS = 5 V |
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td sc / ms |
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BUK102-50GL |
10 |
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PDSM |
1 |
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0.1 |
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0.1 |
1 |
10 |
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PDS / kW |
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Fig.12. Typical overload protection characteristics. |
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td sc = f(PDS); conditions: VIS |
³ 4 V; Tj = 25 ˚C. |
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PDSM% |
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120 |
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100 |
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80 |
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60 |
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40 |
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20 |
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0 |
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-60 |
-40 |
-20 |
0 |
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60 |
80 |
100 |
120 |
140 |
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Tmb / C |
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Fig.13. Normalised limiting overload dissipation. PDSM% =100×PDSM/PDSM(25 ˚C) = f(Tmb)
January 1993 |
6 |
Rev 1.200 |
Philips Semiconductors |
Product specification |
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PowerMOS transistor |
BUK102-50GL |
Logic level TOPFET |
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Energy & Time |
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BUK102-50GL |
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1.5 |
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Energy / J |
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1.0 |
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Time / ms |
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0.5 |
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Tj(TO) |
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0 |
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-60 |
-20 |
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100 |
140 |
180 |
220 |
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Tmb / C |
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Fig.14. Typical overload protection characteristics. Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mW
ID / A |
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BUK102-50GL |
50 |
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40 |
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30 |
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typ. |
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20 |
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10 |
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0 |
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50 |
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60 |
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70 |
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VDS / V |
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Fig.15. Typical clamping characteristics, 25 ˚C. |
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ID = f(VDS); conditions: VIS = 0 V; tp |
£ 50 ms |
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VIS(TO) / V |
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2 |
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max. |
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typ. |
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1 |
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min. |
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0 |
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-60 |
-40 |
-20 |
0 |
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40 |
60 |
80 |
100 |
120 140 |
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Tj / |
C |
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Fig.16. |
Input threshold voltage. |
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VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V |
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IIS / uA |
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BUK102-50GL |
500 |
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400 |
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300 |
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200 |
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100 |
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0 |
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0 |
2 |
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6 |
8 |
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VIS / V |
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Fig.17. Typical DC input characteristics, Tj = 25 ˚C. IIS = f(VIS); normal operation
IIS / mA |
BUK102-50GL |
5
PROTECTION LATCHED
4 |
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3 |
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RESET |
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2 |
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1 |
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NORMAL |
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0 |
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0 |
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2 |
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4 |
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6 |
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8 |
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VIS / V |
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Fig.18. |
Typical DC input characteristics, Tj = 25 ˚C. |
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IISL = f(VIS); overload protection operated Þ ID = 0 A |
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IS / A |
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BUK102-50GL |
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200 |
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150 |
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100 |
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50 |
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0 |
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0 |
0.2 |
0.4 |
0.6 |
0.8 |
1 |
1.2 |
1.4 |
1.6 |
1.8 |
2 |
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VSD / V |
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Fig.19. Typical reverse diode current, Tj = 25 ˚C. IS = f(VSDS); conditions: VIS = 0 V; tp = 250 ms
January 1993 |
7 |
Rev 1.200 |
Philips Semiconductors |
Product specification |
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PowerMOS transistor |
BUK102-50GL |
Logic level TOPFET |
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VDD |
RL |
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TOPFET |
D |
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I |
D.U.T. |
P |
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RI |
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VIS |
S |
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ID measure |
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0V |
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0R1 |
Fig.20. Test circuit for resistive load switching times.
RESISTIVE TURN-ON |
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BUK102-50GL |
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15 |
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VDS / V |
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ID / A |
10 |
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90% |
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td on |
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tr |
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VIS / V |
5 |
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10% |
10% |
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0 |
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10 |
20 |
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Time / us |
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Fig.21. Typical switching waveforms, resistive load. |
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VDD = 13 V; RL = 1.1 |
Ω; RI = 50 |
Ω, Tj = 25 ˚C. |
RESISTIVE TURN-OFF |
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BUK102-50GL |
15 |
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VDS / V |
ID / A |
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10 |
90% |
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td off |
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VIS / V |
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tf |
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5 |
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90% |
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10% |
0 |
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0 |
10 |
20 |
Time / us
Fig.22. Typical switching waveforms, resistive load. VDD = 13 V; RL = 1.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
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VDD = VCL |
LD |
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t p : adjust for correct ID |
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TOPFET |
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I |
D.U.T. |
P |
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R I |
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VIS |
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ID measure |
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0V |
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0R1 |
Fig.23. Test circuit for inductive load switching times.
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INDUCTIVE TURN-ON |
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BUK102-50GL |
10 |
VDS / V |
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ID / A |
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90% |
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td on |
tr |
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VIS / V |
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10% |
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10% |
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0 |
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20 |
Time / us
Fig.24. Typical switching waveforms, inductive load. |
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VDD = 13 V; ID = 11 A; RI = 50 |
Ω, Tj = 25 ˚C. |
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INDUCTIVE TURN-OFF |
BUK102-50GL |
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ID / A |
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10 |
90% |
VDS / V |
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td off |
tf |
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90% |
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VIS / V |
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10% |
0 |
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-1 |
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0 |
10 |
20 |
Time / us
Fig.25. Typical switching waveforms, inductive load. VDD = 13 V; ID = 11 A; RI = 50 Ω, Tj = 25 ˚C.
January 1993 |
8 |
Rev 1.200 |
Philips Semiconductors |
Product specification |
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PowerMOS transistor |
BUK102-50GL |
Logic level TOPFET |
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EDSM% |
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120 |
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110 |
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100 |
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90 |
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80 |
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70 |
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60 |
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50 |
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40 |
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30 |
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20 |
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10 |
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0 |
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0 |
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Tmb / C |
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Fig.26. Normalised limiting clamping energy. |
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EDSM% = f(Tmb); conditions: ID = 25 A; VIS = 10 V |
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VDS |
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V(CL)DSS |
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VDD |
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VDD |
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ID |
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L |
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0 |
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VDS |
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VIS |
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D |
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TOPFET |
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-ID/100 |
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0 |
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D.U.T. |
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Schottky |
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R 01 |
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RIS |
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S |
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shunt |
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Fig.27. |
Clamping energy test circuit, RIS |
= 50 Ω. |
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E |
DSM |
= 0.5 × LI2 |
× V |
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(CL )DSS |
- V |
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D |
(CL )DSS |
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DD |
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Idss |
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1 mA |
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100 uA |
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10 uA |
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typ. |
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1 uA |
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100 nA |
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0 |
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Tj / C |
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Fig.28. Typical off-state leakage current. IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V.
Iiso normalised to 25 C
1.5 |
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1 |
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0.5 |
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-60 |
-20 |
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100 |
140 |
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Tj / C |
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Fig.29. Normalised input current (normal operation). IIS/IIS25 ˚C = f(Tj); VIS = 5 V
Iisl normalised to 25 C
1.5 |
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1 |
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0.5 |
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-60 |
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100 |
140 |
180 |
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Tj / C |
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Fig.30. Normalised input current (protection latched). IISL/IISL25 ˚C = f(Tj); VIS = 5 V
January 1993 |
9 |
Rev 1.200 |
Philips Semiconductors Product specification
PowerMOS transistor |
BUK102-50GL |
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Logic level TOPFET |
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MECHANICAL DATA |
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Dimensions in mm |
4,5 |
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Net Mass: 2 g |
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max |
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10,3 |
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max |
1,3 |
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3,7 |
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2,8 |
5,9 |
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min |
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15,8 |
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max |
3,0 max |
3,0 |
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not tinned |
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13,5 |
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min |
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1,3 |
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max |
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(2x) |
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0,9 max (3x) |
0,6 |
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2,54 2,54 |
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2,4 |
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Fig.31. TO220AB; pin 2 connected to mounting base.
Notes
1.Accessories supplied on request: refer to mounting instructions for TO220 envelopes.
2.Epoxy meets UL94 V0 at 1/8".
January 1993 |
10 |
Rev 1.200 |