Материал: 4HC4351

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MC54/74HC4351 MC54/74HC4353
(OHMS)	250										(OHMS)	100
(OHMS)	200										(OHMS)	80
RESISTANCE	200								125°C		RESISTANCE	80
									125°C
	150								25°C			60
									25°C

, ON	100										, ON	40
, ON									± 55°C		, ON
on									± 55°C		on
R	50										R	20
	50											20
	0	0.25	0.50	0.75	1.0	1.25	1.5	1.75	2.0	2.25
		VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

								125°C
								25°C
								± 55°C
0	0.5	1.0	1.5	2.0	2.5	3.0	3.5	4.0	4.5
	VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

	Figure 1a. Typical On Resistance, VCC ± VEE = 2.0 V														Figure 1b. Typical On Resistance, VCC ± VEE = 4.5 V
(OHMS)	105													(OHMS)	75
												°			75								125°C
												°											125°C
	90											125 C
	90
															60
RESISTANCE	75											25°C		RESISTANCE	60								25°C
	75																						25°C

	60														45
	45											± 55°C											± 55°C
, ON	45													, ON	30								± 55°C
															30
	30
on	30													on
R														R	15
	15														15
	15
	0	0.5	1.0	1.5	2.0	2.5	3.0	3.5	4.0	4.5	5.0	5.5	6.0		0	1.0	2.0	3.0	4.0	5.0	6.0	7.0	8.0	9.0
		VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE														VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
	Figure 1c. Typical On Resistance, VCC ± VEE = 6.0 V														Figure 1d. Typical On Resistance, VCC ± VEE = 9.0 V
																		PLOTTER
(OHMS)	70
	60											125°C		PROGRAMMABLE
														PROGRAMMABLE
															POWER		MINI COMPUTER					DC ANALYZER
RESISTANCE	50											25°C			POWER		MINI COMPUTER					DC ANALYZER
	50											25°C			SUPPLY
															SUPPLY
	40														±	+					VCC
															±	+
												± 55°C
	30																	DEVICE
, ON	30

	20																	UNDER TEST
on																		UNDER TEST
on
R
	10															ANALOG IN					COMMON OUT
	0	1.0	2.0	3.0	4.0	5.0	6.0	7.0	8.0	9.0	10.0	11.0	12.0				GND			VEE
		VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE															GND			VEE
		VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE

Figure 1e. Typical On Resistance, VCC ± VEE = 12.0 V

Figure 2. On Resistance Test Set±Up

MOTOROLA

MC54/74HC4351 MC54/74HC4353

VCC

				VCC			VCC
VEE			20		VEE		20
	ANALOG I/O					ANALOG I/O
		OFF
	A					OFF	A
VCC		OFF		COMMON O/I	VCC	OFF
	NC						COMMON O/I

VIH	7	VIH	7
	8		8
	9		9
	10		10
VEE		VEE

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set±Up

VCC			VCC
	A	20	VCC
		20

	ON		N/C
	OFF		N/C
VEE	OFF		COMMON O/I
VEE	ANALOG I/O
VCC	ANALOG I/O
VCC

VIL 7

VIH 8 9

VEE

Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set±Up

Figure 4. Maximum Off Channel Leakage Current,

Common Channel, Test Set±Up

	VCC VOS
μ	20	dB
0.1 F		dB
fin	ON	METER
	CL*	RL
VCC
	7
	8
	9
	10
VEE

*Includes all probe and jig capacitance.

Figure 6. Maximum On Channel Bandwidth,

Test Set±Up

	VIS	VCC	VOS				VCC
0.1	μ	20					20
0.1	F			dB	RL
fin				dB	RL
fin		OFF		METER		ON/OFF	COMMON O/I		TEST
			CL*	RL	ANALOG I/O				TEST
	R				ANALOG I/O				POINT
	R							CL*	POINT
	L					OFF/ON	R	CL*
					RL		L
					RL
		7			VCC	7
		8			VCC	7
		8				8
		9				8		VCC
		9				9		VCC
		10			Vin ≤ 1 MHz	9	11
		10			Vin ≤ 1 MHz	10	11
	V				tr = tf = 6 ns
	EE			VCC	VEE
				GND		CHANNEL SELECT
						CHANNEL SELECT

*Includes all probe and jig capacitance.

Figure 7. Off Channel Feedthrough Isolation,	Figure 8. Feedthrough Noise, Channel Select to
Test Set±Up	Common Out, Test Set±Up

MOTOROLA

MC54/74HC4351 MC54/74HC4353

tr		tf
	90%	VCC
CHANNEL SELECT	90%
CHANNEL SELECT	50%
	10%	GND
		GND
tPLH		tPHL
ANALOG OUT	50%
ANALOG OUT

Figure 9a. Propagation Delays, Channel Select

to Analog Out

ANALOG	VCC
IN	50%
	50%
	GND
tPLH	tPHL
ANALOG
OUT	50%
	50%

Figure 10a. Propagation Delays, Analog In to Analog Out

ENABLE	50%		VCC

			GND
	tPZL	tPLZ	HIGH
ANALOG
	50%		IMPEDANCE
OUT
		10%	VOL
	tPZH
		tPHZ	VOH
ANALOG	50%	90%
			HIGH
OUT

			IMPEDANCE

Figure 11a. Propagation Delay, Enable 1 or 2 to Analog Out

VCC	VCC
	20
ON/OFF	COMMON O/I	TEST
ANALOG I/O		TEST
ANALOG I/O		POINT
OFF/ON	CL*	POINT
OFF/ON
VCC
VCC
7
8
9
10

CHANNEL SELECT

*Includes all probe and jig capacitance.

Figure 9b. Propagation Delay, Test Set±Up Channel Select to Analog Out

		VCC
		20
ANALOG I/O		COMMON O/I
	ON	TEST
	ON	POINT
		POINT
VCC		CL*
VCC
	7
	8
	9
	10

*Includes all probe and jig capacitance.

Figure 10b. Propagation Delay, Test Set±Up Analog In to Analog Out

	POSITION		1 WHEN TESTING tPHZ AND tPZH
1	POSITION		2 WHEN TESTING tPLZ AND tPZL
1
2			VCC
VCC			VCC
VCC			20	Ω
			20	1 k
1	ANALOG I/O			TEST
2			ON/OFF	TEST
			ON/OFF	POINT
				POINT
				CL*
	ENABLE	7
	ENABLE	8
		8
		9
		10

Figure 11b. Propagation Delay, Test Set±Up

Enable to Analog Out

MOTOROLA

MC54/74HC4351 MC54/74HC4353

CHANNEL			VCC
CHANNEL	50%
SELECT	50%
SELECT			GND
			GND
	tsu	tf	th
	tr	tf	VCC
LATCH	90%		VCC
LATCH	50%
ENABLE 2	50%
ENABLE 2	10%		GND
	10%

	tw
COMMON O/I		50%
	tPLH,
	tPHL

Figure 12a. Propagation Delay, Latch Enable to Analog Out

VIS

VCC

	RL		20			VOS
fin	RL		ON			VOS
fin			ON
0.1 μF						dB
						METER
			OFF
VCC	VEE	R	R	C *	R	C *
		L	R	C *	R	C *
			L	L	L	L
			7
			8
			9
			10

*Includes all probe and jig capacitance.

Figure 13. Crosstalk Between Any Two

Switches, Test Set±Up

	VCC
VCC	20
ON/OFF	COMMON O/I	TEST
ANALOG I/O		TEST
ANALOG I/O		POINT
OFF/ON	CL*	POINT
OFF/ON
VCC
VCC
7
8
9
10	11
LATCH ENABLE

CHANNEL SELECT

*Includes all probe and jig capacitance.

Figure 12b. Propagation Delay, Test Set±Up Latch Enable to Analog Out

VCC

	VCC	A
	VCC	20
		20
	ON/OFF	NC
	ANALOG I/O	NC
	OFF/ON	COMMON O/I
	VCC
	7	VCC
	8	VCC
	9
	10	11
	VEE

CHANNEL SELECT

Figure 14. Power Dissipation Capacitance,

Test Set-Up

						0
			VIS			± 10	FUNDAMENTAL FREQUENCY
			VCC	V		± 20
	μ		20	OS		± 20
0.1	μ	F	20		TO	± 30
0.1		F
fin			ON
fin			ON		DISTORTION	± 40
			RL	C *	METER	± 40
			RL	C *	METER
				L	dB	± 50
VCC					dB	± 50	DEVICE
VCC						± 60	DEVICE
			7			± 60	SOURCE
			7			± 70	SOURCE
			8			± 70
			9			± 80
			10			± 80
			10			± 90
VEE						± 90
VEE
*Includes all probe and jig capacitance.						1.0	2.0	3.125
*Includes all probe and jig capacitance.							FREQUENCY (kHz)
							FREQUENCY (kHz)

Figure 15a. Total Harmonic Distortion, Test Set-Up

Figure 15b. Plot, Harmonic Distortion

MOTOROLA

MC54/74HC4351 MC54/74HC4353

APPLICATIONS INFORMATION

The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example:

VCC = + 5 V = logic high

GND = 0 V = logic low

The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration in Figure 16, a maximum analog signal of ten volts peak±to±peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). How-

ever, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch.

Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that:

VCC ± GND = 2 to 6 volts

VEE ± GND = 0 to ± 6 volts

VCC ± VEE = 2 to 12 volts

and VEE v GND

When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 17. These diodes should be able to absorb the maximum anticipated current surges during clipping.

			+5 V		VCC	VCC	V
			+5 V			VCC	CC
+ 5 V		20		+ 5 V	Dx	20	D
+ 5 V	ANALOG		ANALOG	+ 5 V			x
	ANALOG	ON	ANALOG			ON/OFF
	SIGNAL	ON	SIGNAL			ON/OFF
± 5 V	SIGNAL		SIGNAL	± 5 V	Dx
± 5 V				± 5 V			D
							D
							x
	+ 5 V				VEE		V
	7	15	TO EXTERNAL CMOS				EE
	7	15	TO EXTERNAL CMOS
	8	13	CIRCUITRY
	9	12	0 TO 5 V DIGITAL			9
	10	11	SIGNALS			10
	± 5 V				VEE
					VEE
	Figure 16. Application Example				Figure 17. External Germanium or

Schottky Clipping Diodes

			+ 5 V
+ 5 V		20	ANALOG			+ 5 V	+ 5 V
+ 5 V						+ 5 V	+ 5 V
ANALOG	ON/OFF
SIGNAL	ON/OFF		SIGNAL
SIGNAL			SIGNAL			VEE	VEE
VEE				+ 5 V		VEE	VEE
			*
VCC			R	R	R	R
VCC
	7	15				LSTTL/NMOS
	8	13				LSTTL/NMOS
	9	12				CIRCUITRY
	10	11
VEE			* 2 k ≤ R ≤ 10 k
VEE

a. Using Pull±Up Resistors

			+ 5 V
ANALOG		20	ANALOG	+ 5 V
				+ 5 V
	ON/OFF
SIGNAL	ON/OFF		SIGNAL
SIGNAL			SIGNAL	VEE
				VEE
VCC				+ 5 V
VCC	7	15
	8	13		LSTTL/NMOS
	9	12		CIRCUITRY
	10	11
VEE			HCT
VEE			BUFFER
			BUFFER

b. Using HCT Interface

Figure 18. Interfacing LSTTL/NMOS to CMOS Inputs

MOTOROLA

Источник: https://studfile.net/preview/16503021/

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