Материал: TC7106

GENERAL THEORY OF OPERATION DUAL SLOPE CONVERSION PRINCIPLES

(All Pin Designations Refer to the 40-Pin DIP)

The TC7106A and TC7107A are dual slope, integrating analog-to-digital converters. An understanding of the dual slope conversion technique will aid in following the detailed operation theory.

The conventional dual slope converter measurement cycle has two distinct phases:

•Input Signal Integration

•Reference Voltage Integration (Deintegration)

The input signal being converted is integrated for a fixed time period (TSI). Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (TRI). (Figure 2A).

In a simple dual slope converter a complete conversion requires the integrator output to “ramp-up” and “rampdown.”

A simple mathematical equation relates the input signal, reference voltage and integration time:

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where:

VR = Reference Voltage

TSI = Signal Integration Time (Fixed)

TRI = Reference Voltage Integration Time (Variable)

For a constant VIN:

TRI

TSI

FIXED VARIABLE

SIGNAL REFERENCE

INTEGRATE INTEGRATE

TIME TIME

Figure 2A. Basic Dual Slope Converter

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The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Noise spikes are integrated or averaged to zero during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50/60 Hz power line period. (Figure 2B)

Figure 2B. Normal-Mode Rejection of Dual Slope Converter

ANALOG SECTION

In addition to the basic signal integrate and deintegrate cycles discussed, the circuit incorporates an auto-zero cycle. This cycle removes buffer amplifier, integrator, and comparator offset voltage error terms from the conversion. A true digital zero reading results without adjusting external potentiometers. A complete conversion consists of three cycles: an auto-zero, signal-integrate and reference-inte- grate cycle.

Auto-Zero Cycle

During the auto-zero cycle the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero-input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on CAZ compensates for device offset voltages. The offset error referred to the input is less than 10μV.

The auto-zero cycle length is 1000 to 3000 counts.

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Signal Integrate Cycle

When the auto-zero loop is opened, the internal differential inputs connect to VIN+ and VIN– . The differential input signal is integrated for a fixed time period. The signal integration period is 1000 counts. The externally set clock frequency is divided by four before clocking the internal counters. The integration time period is:

where:

fOSC = External Clock Frequency

The differential input voltage must be within the device common-mode range (1V of either supply) when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, VIN– should be tied to analog common.

Polarity is determined at the end of the signal integrate phase. The sign bit is a true polarity indication in that signals less than 1 LSB are correctly determined. This allows precision null detection, limited only by device noise and auto-zero residual offsets.

Reference Integrate Cycle

The final phase is reference integrate or de-integrate. VIN– is internally connected to analog common and VIN+ is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 counts. The digital reading displayed is:

VIN

1000 x VREF

DIGITAL SECTION (TC7106A)

The TC7106A (Figure 3) contains all the segment drivers necessary to directly drive a 3 -1/2 digit liquid crystal display (LCD). An LCD backplane driver is included. The backplane frequency is the external clock frequency divided by 800. For three conversions/second the backplane frequency is 60Hz with a 5V nominal amplitude. When a segment driver is in phase with the backplane signal the segment is “OFF.” An out of phase segment drive signal causes the segment to be “ON” or visible. This AC drive configuration results in negligible DC voltage across each LCD segment. This insures long LCD display life. The polarity segment driver is “ON” for negative analog inputs. If VIN+ and VIN– are reversed, this indicator will reverse.

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Diagram Block TC7106A .3 Figure

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TYPICAL SEGMENT OUTPUT

V+

CONVERTERS A/D DIGIT 1/2-3

When the TEST pin on the TC7106A is pulled to V+, all segments are turned “ON.” The display reads –1888. During this mode the LCD segments have a constant DC voltage impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE FOR MORE THAN SEVERAL MINUTES! LCD displays may be destroyed if operated with DC levels for extended periods.

The display font and the segment drive assignment are shown in Figure 4.

DISPLAY FONT

Figure 4. Display Font and Segment Assignment

In the TC7106A, an internal digital ground is generated from a 6 volt zener diode and a large P channel source follower. This supply is made stiff to absorb the large capacitive currents when the backplane voltage is switched.

DIGITAL SECTION (TC7107A)

Figure 5 shows the TC7107A. It is designed to drive common anode LEDs. It is identical to the TC7106A except that the regulated supply and backplane drive have been eliminated and the segment drive is typically 8mA. The 1000's output (pin 19) sinks current from two LED segments, and has a 16mA drive capability.

In both devices, the polarity indication is “ON” for negative analog inputs. If VIN– and VIN+ are reversed, this indication can be reversed also, if desired.

The display font is the same as the TC7106A.

System Timing

The oscillator frequency is divided by 4 prior to clocking the internal decade counters. The three-phase measurement cycle takes a total of 4000 counts or 16000 clock pulses. The 4000 count cycle is independent of input signal magnitude.

Each phase of the measurement cycle has the following length:

•Auto-Zero Phase: 1000 to 3000 Counts

(4000 to 12000 Clock Pulses)

For signals less than full-scale, the auto-zero phase is assigned the unused reference integrate time period.

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•Signal Integrate: 1000 Counts

TSI = 4000 [ fOSC1 ]

Where fOSC is the externally set clock frequency.

•Reference Integrate: 0 to 2000 Counts

TO TEST PIN ON TSC7106A

TO GND PIN ON TSC7107A

Figure 6. Clock Circuits

The reference voltage used to ramp the integrator output voltage back to zero during the reference-integrate cycle is stored on CREF. A 0.1mF capacitor is acceptable when VIN– is tied to analog common. If a large common-mode voltage exists (VREF– ¹ analog common) and the application

requires 200mV full-scale, increase CREF to 1.0 mF. Rollover 8 error will be held to less than 1/2 count. A mylar dielectric capacitor is adequate.

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.INC SEMICONDUCTOR,

CONVERTERS A/D DIGIT 1/2-3