Материал: mrf175lurev8

VDD = 28 V, IDQ = 100 mA, (Pout = 100 W)

ZOL* = CONJUGATE OF THE OPTIMUM LOAD IMPEDANCE INTO WHICH THE DEVICE OUTPUT OPERATES AT A GIVEN

OUTPUT POWER, VOLTAGE AND FREQUENCY.

MOSFET CAPACITANCES

The physical structure of a MOSFET results in capacitors between the terminals. The metal oxide gate structure determines the capacitors from gate±to±drain (Cgd), and gate±to± source (Cgs). The PN junction formed during the fabrication of the FET results in a junction capacitance from drain±to±

source (Cds).

These capacitances are characterized as input (Ciss), output (Coss) and reverse transfer (Crss) capacitances on data sheets. The relationships between the inter±terminal capacitances and those given on data sheets are shown below. The Ciss can be specified in two ways:

1.Drain shorted to source and positive voltage at the gate.

2.Positive voltage of the drain in respect to source and zero volts at the gate. In the latter case the numbers are lower. However, neither method represents the actual operating conditions in RF applications.

LINEARITY AND GAIN CHARACTERISTICS

In addition to the typical IMD and power gain data presented, Figure 3 may give the designer additional information on the capabilities of this device. The graph represents the small signal unity current gain frequency at a given drain cur-

rent level. This is equivalent to fT for bipolar transistors. Since this test is performed at a fast sweep speed, heating of the device does not occur. Thus, in normal use, the higher temperatures may degrade these characteristics to some extent.

DRAIN CHARACTERISTICS

One figure of merit for a FET is its static resistance in the full±on condition. This on±resistance, VDS(on), occurs in the linear region of the output characteristic and is specified under specific test conditions for gate±source voltage and drain current. For MOSFETs, VDS(on) has a positive temperature coefficient and constitutes an important design consideration at high temperatures, because it contributes to the power dissipation within the device.

GATE CHARACTERISTICS

The gate of the FET is a polysilicon material, and is electrically isolated from the source by a layer of oxide. The input resistance is very high Ð on the order of 10 9 ohms Ð resulting in a leakage current of a few nanoamperes.

Gate control is achieved by applying a positive voltage slightly in excess of the gate±to±source threshold voltage,

VGS(th).

Gate Voltage Rating Ð Never exceed the gate voltage rating. Exceeding the rated VGS can result in permanent damage to the oxide layer in the gate region.

Gate Termination Ð The gates of these devices are essentially capacitors. Circuits that leave the gate open±circuited or floating should be avoided. These conditions can result in turn±on of the devices due to voltage build±up on the input capacitor due to leakage currents or pickup.

Gate Protection Ð These devices do not have an internal monolithic zener diode from gate±to±source. If gate protection is required, an external zener diode is recommended.

Using a resistor to keep the gate±to±source impedance low also helps damp transients and serves another important function. Voltage transients on the drain can be coupled to the gate through the parasitic gate±drain capacitance. If the gate±to±source impedance and the rate of voltage change on the drain are both high, then the signal coupled to the gate may be large enough to exceed the gate±threshold voltage and turn the device on.

HANDLING CONSIDERATIONS

When shipping, the devices should be transported only in antistatic bags or conductive foam. Upon removal from the packaging, careful handling procedures should be adhered to. Those handling the devices should wear grounding straps and devices not in the antistatic packaging should be kept in metal tote bins. MOSFETs should be handled by the case and not by the leads, and when testing the device, all leads should make good electrical contact before voltage is applied. As a final note, when placing the FET into the system it is designed for, soldering should be done with a grounded iron.

DESIGN CONSIDERATIONS

The MRF175L is a RF power N±channel enhancement mode field±effect transistor (FETs) designed for HF, VHF and UHF power amplifier applications. Motorola FETs feature a vertical structure with a planar design.

Motorola Application Note AN211A, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs.

The major advantages of RF power FETs include high gain, low noise, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can be varied over a wide range with a low power dc control signal.

DC BIAS

The MRF175L is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied. Drain current flows when a positive voltage is applied to the gate. RF power FETs require forward bias for optimum performance. The value of quiescent drain current (IDQ) is not critical for many applications. The MRF175L was characterized at IDQ = 100 mA, each side, which is the suggested minimum value of IDQ. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical parameters.

The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may be just a simple resistive divider network. Some applications may require a more elaborate bias sytem.

GAIN CONTROL

Power output of the MRF175L may be controlled from its rated value down to zero (negative gain) by varying the dc gate voltage. This feature facilitates the design of manual gain control, AGC/ALC and modulation systems.