Документ: spra118, страницы 11-15 | База учебных материалов

SPRA118

Secondly, a synchronous coding adjustment module is included at the output of the decoder. It finds its origin in the non-reciprocity between linear PCM word (14 bits) and logarithmic PCM word (8 bits). The problem, for the decoder, is to choose a log-PCM output word, SD, that is actually representative of the ADPCM input word I. This means that if you give SD as the input encoder, you also have to find I as output. This feature is already ensured for the linear PCM output word, because of the feedback of the ADPCM quantization error in signal estimation (the encoder also includes a decoding module). However, this property is no longer ensured after converting linear PCM into log-PCM, due to the error of this logarithmic quantization. The synchronous coding adjustment module ensures that this feature is maintained. This allows multiple encoding-decoding-encoding without adding distortion.

As shown below, these format conversions and corrections are implemented in the C54x for both G.726 and G.711 recommendations. The routines are valid for either A-law or m-law. Tables and specific variables make the distinction between the two.

3.1.1Log-PCM Companding

This module converts a linear PCM word into the logarithmic domain. As you saw, a word coming from A-law has been one bit left-shifted, to get the maximum resolution in the ADPCM algorithm. Now you have to do the reverse transformation before converting it to A-law. This transformation includes rounding for negative words by subtracting one from the magnitude before right-shifting. When considering that for small signals (t 64) a linear quantization is required for A-law simply by dividing sample magnitude by two, the total right shift to apply for A-law is thus 2 bits. For A-law large signals, this 2-bit right shift is also applied, and then compensated further.

Use the variable LAWBIAS (= 33 for m-law, = 0 for A-law). Added to the linear PCM word, this variable allows you to use powers of two as quantizer decision values. For m-law also, it avoids the need to branch to linear quantization, which is required for magnitudes smaller than 32.

The logarithm calculation is quickly performed using the EXP and NORM instructions. See § () for the method. The first difference is that normalization is done in Q4 format instead of Q7. As you compute logarithmically only for large magnitudes (w 32), you decrease the dynamic by storing only the segment of the word. This segment is defined by:

segment = (exponent – 1) – segment offset,

where exponent is defined in section 3.2.1 or in section 3.43

This makes it possible to code it with only three bits instead of four. The variable LAWSEG allows us to complete the logarithm transformation, including the segment offset (4 for A-law, 5 for m-law) and the compensation left shift for A-law (see above).

Restore the sign to the magnitude by adding 128 for positive PCM words. Lastly, invert bits (only even bits for A-law), to satisfy transmission practices; this is done by means of the variable LAWMASK (0x55 for A-law, 0x7F for m-law).

The companding routine is shown below, with the section of code added specifically to meet the requirements of G.726 highlighted in bold characters. The rest is sufficient for G.711. When code shown in italic characters is suppressed, the routine performs m-law compression in only 13 cycles.

18 G.726 Adaptive Differential Pulse Code Modulation (ADPCM) on the TMS320C54x DSP

				SPRA118
***********************************************************************************
* Converts signal from uniform PCM to a A-law or Mu-law PCM signal with format				*
* correction				*
*				*
*	INPUT:			*
* A		= SR(k) Reconstructed signal		*
* LAW		= LAW (0 for Mu-law, 1 for A-law)		*
* LAWBIAS		= Bias constant (=0 for A-law, =33 for Mu-law)		*
* LAWSEG		= Constant in order to compute the segment of the PCM word		*
* LAWMASK		= Magnitude mask for A-law or Mu-law PCM word		*
*				*
*	OUTPUT:			*
* SD = A		= SP(k) A-law or Mu-law PCM reconstructed signal		*
*				*
*	CYCLES:		Min: 20, Max: 26	*
*			only G711: 21	*
*			only m-law: 13	*
***********************************************************************************
SYNC	STH	A, *AR5	; Store sign of SR
	BIT	*AR5, 0	; TC = 0 if SR positive
	LD	LAW, B	; If LAW = 1: A-law
	ABS	A	; A = \|SR\| = IM
	AND	C32767, A	; If RATE = 40, SR = 8000 can occur: overflow
	XC	1, ALT	;
	SUB	LAW, A	; If SR < 0, subtract 1 to IM for A-law
	ABS	A	; Ensures A positive (case SR = 8000)
	XC	1, BNEQ	; A-law: one shift for 12-bit unsigned word,
	SFTA	A, -2	; and one shift for linear quantization (SFTA A, -1 for G.711)
	ADD	LAWBIAS, A	; Add Bias
	SUB	C32, A, B	;
	BC	ECOMP, BLT	; Linear quantization for A-law if IMAG < 32
	EXP	A	; TREG = 31 – EXP
	LD	LAWSEG, B	; LAWSEG =24*2^4 for Mu-law and TREG latency
	NORM	A	; A = (SR << (15-EXP)) << 16
	SFTA	A, –10	; A = (SR << (4–(EXP–1))) << 16
	MAS	C16, B	; B = 242^4 – (TREG2^4) = (EXP–7) << 4
	ADD	A, –16, B ; B = \|SP\|
	LD	C127, A	; Load SPmax
	MIN	A	; Saturate if \|SR\| out of range
ECOMP XC		1, NTC	; Test if SR positive
		G.726 Adaptive Differential Pulse Code Modulation (ADPCM) on the TMS320C54x DSP			19

SPRA118

ADD	C128,	A	; Add bit sign if positive
XOR	LAWMASK, A		; Apply law mask
STL	A, SD		; SD = SP = A-law or Mu-law PCM word

Note that in logarithmic calculation, you use (exponent – 1), instead of segment (see section 3.4).

3.1.2Linear PCM Expanding

This module converts a PCM word from logarithmic domain to linear domain.

To reduce the clock cycles timing, tables are used for this PCM expansion. As outputs levels are symmetrical relative to zero, use the magnitude of the log-PCM word as an offset table. This property limits the table to 128 words. One table is used for the A-law PCM (ALAW), and another is used for m-law PCM (MULAW). As you saw above, the A-law table directly gives the magnitude of the linear PCM word multiplied by two, making it a 13-bit unsigned number as required.

The original sign is then introduced, so that these samples are now in 14-bit, two-complement format.

The routine shown here executes in 13 cycles; two of these cycles can be used to execute initialization instructions for the following blocks. For example, if you perform G.726 ADPCM without linear capability, this routine is always performed, so you can, for example, replace the NOP instructions by the initialization of the block repeat counter BRC, used for the ADPCM quantization (see section 3.5).

***************************************************************************************

*Converts signal from A-law or Mu-law PCM to uniform PCM signal with format correction*

*				*
*	INPUT:			*
* A		= S(k) input signal (encoding)		*
*		= SP(k) A-law or Mu-law reconstructed signal (decoding)		*
* LAWMASK		= Magnitude mask for A-law or Mu-law PCM word		*
* ADLAW		= Law table address in Data-ROM		*
* xLAW (*AR2)= Law inverse quantizing table (x = MU or A)				*
*				*
*	OUTPUT:			*
* A		= SL(k) linear input signal (encoding)		*
*		= SLX(k) linear output signal (decoding)		*
*				*
*	CYCLES: 13(actually 11 if replacing NOP latency by instructions of other blocks)*
***********************************************************************************
EXPAN XOR		LAWMASK, A	; Invert even bits if A-law
	SFTA	A, –7, B	; B = 1 if SP positive, 0 if SP negative
	AND	C127, A	; A = unsigned magnitude
	ADDS	ADLAW, A	; ADLAW = address of inverse log quantizer
	STLMA, AR2		; AR2 = address of linear PCM word

20 G.726 Adaptive Differential Pulse Code Modulation (ADPCM) on the TMS320C54x DSP

	SPRA118
NOP	; AR2 update latency. If this routine is always performed,
NOP	; replace NOP by instructions of other blocks
	; (e.g: initializations)
LD *AR2, A	; A = linear PCM magnitude
RETD	;
XC 1, BEQ	; Convert A in two-complement,
NEG A	; depending on original sign of A

3.1.3Synchronous Coding Adjustment

The synchronous coding adjustment is performed at the end of the decoder module by re-encoding the output PCM word SP and comparing the new code ID with the original ADPCM word I.

This re-encoding is performed by using the same code routines as those used for the encoder (PCM expanding, difference signal calculation, logarithm conversion, adding quantizer scale factor, then quantization). I format is two-complement, but only with the assigned bits for it (2, 3, 4, or 5), and without sign extension along the 16 bits of the processor. So this format is changed, by using a table, to make the comparison with ID possible.

•If ID u I, then SP is overestimated, so choose SP – 1 as new value of SP.

•If ID t I, then SP is underestimated, so choose SP + 1 as new value of SP.

•Otherwise, SP is correctly estimated, and keeps its value.

Note that SP is a signed magnitude, and not two-complement. This does not allow you to perform normal arithmetic. For instance, SP + 1 when SP is negative and is obtained with SP – 1.

Another point is that log-PCM format includes two different values of zero: positive 0 (0+), and negative zero (0–). As a consequence, SP – 1 for SP = 0+ is 0–, and SP + 1 when SP = 0– is 0+. That is only true for A-law; for m-law, SP – 1 for SP = 0+ is –1, and SP + 1 when SP = 0– is +1. 4

Lastly, overflows must be avoided. This means that if SP = 0x7F, then SP + 1 is 0x7F, too. The following code shows a solution for this module (at the time when ID is already calculated).

***********************************************************************************

*	Perform reconstructed signal adjustment		*
*			*
*	INPUT:		*
* B		= ID(k) ADPCM code from re-encoded output PCM sample	*
* IQUAxx (*AR1) = Inverse quantizer table, gives here the magnitude of I (IM)			*
* AR1		= Address of IM in IQUAxx table	*
* SD		= SP(k) A-law or Mu-law PCM reconstructed signal	*
* LAWMASK		= Magnitude mask for A-law or Mu-law PCM word	*
*			*
*	OUTPUT:		*

G.726 Adaptive Differential Pulse Code Modulation (ADPCM) on the TMS320C54x DSP

21

SPRA118

* A	= SD(k) Decoder PCM output word	*
*		*
*	CYCLES: Min: 6 (usual), Max: 25	*

***********************************************************************************

	SUB	*AR1, B		; B = ID – IM
	RCD	BEQ		; If IM =	ID,	SD = SP and do not change SD
	LD	SD, A		; Load output		PCM word
	STH	A, 9,	*AR5	; *AR5 = sign		variable = 1 if SP positive, 0 else
	XOR	LAWMASK, A		; Apply law mask to obtain magnitude of SP
	AND	C127,	A	; A = unsigned magnitude of SP (C127 = 127)
	BC	SP0, AEQ		; \|SP\| = 0 is		a special case: go to SP0
	BIT	*AR5,	15	; Test original sign of SP
	LD	#1, B		; Load gain to prepare SP adjustment
	XC	1, BGT		; If ID >	IM,	case SD = SP–
	NEG	B		; In this	case, negate the gain
	ADD	B, A		; Add the	gain if SP positive
	XC	1, NTC		; TC = 0 if SP negative
	SUB	B, 1,	A	; In this	case, subtract the gain
	LD	C127,	B	; A = \|SD\| is		compared to \|SDmax\|
	MIN	A		; Saturate the result if \|SD\| > 127
	RETD			; Return from		subprogram with A = SD
	ADD	*AR5,	7, A	; Add sign extension
	XOR	LAWMASK, A		; Invert bits		depending on the law
SP0	LD	SIGN,	A	; Case \|SP\| =		0
	AND	LAW, A		; If Mu-Law, LSB of SP is 0
	XOR	C1, A		; SP–(0+)	= –1 for Mu-law, 0– else; and
	XOR	LAWMASK, A		; SP–(0–) = –1 for both laws
	LD	C128,	B	; Load positive sign for SP+ case
	XC	2, BLT		; case SD	= SP+: LSB = 1, only if SIGN = 0
	ADD	LAW, B		; SP+(0–)	= +1 for Mu-law, 0+ else; and
	XOR	B, A		; SP+(0+)	= +1 for both laws
	RET			; A = SD,	NB: B = ID – IM < 0 for SD = SP+

This subtlety is explained in 0.

3.2Floating-Point Features: Conversion, Storage, and Multiplication

The floating-point module concerns the predictor that computes an estimation of the signal by

applying adaptive filters to delayed variables. Coefficients of the predictor filters (a1, a2, bi for i = 1, ..., 6), are between –2 and 2 in Q14 format, while variables (delayed reconstructed

signals sr(k–i) and delayed quantized difference dq(k–i)) are between –32768 and 32767 in Q0 format. All of these variables use a maximum resolution of 16 bits; however, there is a large difference of scale between coefficients and variables.

22 G.726 Adaptive Differential Pulse Code Modulation (ADPCM) on the TMS320C54x DSP

Материал: spra118

3.1.2Linear PCM Expanding

3.1.3Synchronous Coding Adjustment

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