Материал: spra118

SPRA118

A fixed-point multiplication would be inadequate (too much precision for high levels, not enough for low levels). The floating-point format permits better management of the dynamic gaps. Here, the resolution is limited to 6 bits (6 bits mantissa), but the dynamic is greater (0 is coded as 32 (1/2) for mantissa and 0 for exponent). As a consequence, if a variable has a zero value, the floating-point product with the corresponding coefficient would not always be zero, which is always the case with a fixed-point multiplication.

It is described now how floating-point format can be challenged by the C54x for the G.726 recommendation.

3.2.1Floating-Point Format Storage

Floating-point number characteristics are as follows: sign, exponent, mantissa. These features are defined by:

|number| = denormalized mantissa * 2exponent, and sign(number) = sign

If number = 0, this equality is not verified (0 value is coded in floating-point format, as it was actually ½). The following inequalities are verified:

½ v denormalized mantissa t 1. Mantissa is normalized with 6 bits representation, so:

32 v mantissa t 64, where mantissa represents the 6 most significant bits of the fixed-point number, except for zero. As for exponent, you have:

2exponent – 1 v |number| t 2exponent. In practice, the number of the most significant bit plus one (when LSB number is zero).

To make the access faster, use three (successive) words, instead of one, to code a floating-point number: one word for the exponent (Q0 with 4 significant bits), one word for the mantissa (Q6 with 6 significant bits), and one more for the sign (Q0 with 0 significant bits). The sign is coded as an arithmetic sign, and is 0 for positive and null values, –1 for negative values (see section 3.10).

3.2.2Floating-Point Conversion

When loaded into the accumulator, the sign of a word (as defined in section 3.10 ) is the value of the high part of accumulator. The sign is thus extracted, due to the STH instruction. Then, compute the magnitude with the ABS instruction. Now the instructions EXP and NORM are useful for computing exponent and mantissa. EXP calculates the number of non-significant bits relative to the first 32 bits of the accumulator, and stores the result in the temporary register TREG. The wanted value of exponent is thus:

exponent = 31 – TREG for a word different from zero.

When associated with DSUBT that subtracts TREG from a variable that is here set to 31, you directly obtain the value of the exponent (note that DSUBT actually uses a long-word; the high part of this word must be at an even address, while the low part is set to 31).

This method does not apply if the input word to convert is 0. EXP set TREG to zero in this case.

Note also that DSUBT needs one cycle latency to use the TREG value computed by EXP. This feature has been underlined with the evaluation module; however, this latency was unnecessary for the simulator.

SPRA118

Each partial product is limited to 16 bits, which means that the contribution of each one to forming the signal estimate is limited to half of the greatest possible value for the reconstructed signal sr(k). This property is also true for the global signal estimate. However, signal estimate value could reach twice the greatest input PCM value.

The code bellow shows one of the eight floating-point multiplications.

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SPRA118

4.1Algorithm Tables (Program Space)

This section has 849 words and contains six tables. The variables of the involved variables have their format described in Table 30. These tables are:

1.RAM initialization table, INIRAM. This table contains reset values of internal processing variables, and constant values that are transferred in RAM when applying the coder reset routine, _G726ENC_TI_reset or _G726DEC_TI_reset.

2.|I| tables for all rates. Each table contains successively:

a.The lowest level of input quantizer interval, QS|I| (first value of column two, Table 12 through Table 15).

b.The output level of the inverse quantizer, DQLN|I| (column three, Table 16 through Table 19).

c.The rate-of-change weighting function, F|I|, (Table 20 through Table 23).

d.The scale-factor multipliers, W|I| (Table 24 through Table 27).

3.Quantizer tables for all rates. Each table gives the output word that corresponds to a certain level of quantization. For the encoder, it gives the ADPCM word I (in two’s complement, column three of Table 12 through Table 15), and for the decoder (in re-encoding routine for synchronous adjustment), it gives the word ID (in absolute value, column four of Table 12 through Table 15), which has to be compared with the original ADPCM code.

4.Inverse quantizer tables for all rates. Each table gives, from a I ADPCM code, the output level of the quantizer which corresponds to the quantized difference signal (normalized and in logarithmic format, column three, Table 16 through Table 19). It also gives the sign of this quantized difference (column two, Table 16 through Table 19). This sign, which is also the sign of I, is the sign of the original difference signal before being normalized and going into logarithmic domain. Lastly, it gives the word the magnitude of I (column four of Table 16 through Table 19), which has to be compared with ID (see Table 12 through Table 15).

5.A-law and m-law tables for PCM expanding. This inverse quantizer table gives the linear PCM level corresponding to a logarithmic PCM code (see section 3.1.2).

6.PCM laws and coder rate selection tables. These tables permit the initialization of the coder, based on linear PCM, A-law PCM, or m-law PCM choice, and 16, 24, 32, or 40 Kbps coding choice. The relevant variables are those of Table 9.

Table 12. Quantizer Definition for 40-Kbps ADPCM

NOTE: The I values are transmitted with bit 1.