Материал: 18S20

DS18S20

MEMORY FUNCTIONS FLOW CHART Figure 9 (cont’d)

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DS18S20

INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10

DS18S20 COMMAND SET Table 2

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DS18S20

NOTES:

1.Temperature conversion takes up to 750 ms. After receiving the Convert T protocol, if the part does

not receive power from the VDD pin, the DQ line for the DS18S20 must be held high for at least 750 ms to provide power during the conversion process. As such, no other activity may take place on the 1–Wire bus for at least this period after a Convert T command has been issued.

2.After receiving the Copy Scratchpad protocol, if the part does not receive power from the VDD pin, the DQ line for the DS18S20 must be held high for at least 10 ms to provide power during the copy process. As such, no other activity may take place on the 1–Wire bus for at least this period after a Copy Scratchpad command has been issued.

READ/WRITE TIME SLOTS

DS18S20 data is read and written through the use of time slots to manipulate bits and a command word to specify the transaction.

Write Time Slots

A write time slot is initiated when the host pulls the data line from a high logic level to a low logic level. There are two types of write time slots: Write 1 time slots and Write 0 time slots. All write time slots must be a minimum of 60 s in duration with a minimum of a 1- s recovery time between individual write cycles.

The DS18S20 samples the DQ line in a window of 15 s to 60 s after the DQ line falls. If the line is high, a Write 1 occurs. If the line is low, a Write 0 occurs (see Figure 11).

For the host to generate a Write 1 time slot, the data line must be pulled to a logic low level and then released, allowing the data line to pull up to a high level within 15 s after the start of the write time slot.

For the host to generate a Write 0 time slot, the data line must be pulled to a logic low level and remain low for 60 s.

Read Time Slots

The host generates read time slots when data is to be read from the DS18S20. A read time slot is initiated when the host pulls the data line from a logic high level to logic low level. The data line must remain at a low logic level for a minimum of 1 s; output data from the DS18S20 is valid for 15 s after the falling edge of the read time slot. The host therefore must stop driving the DQ pin low in order to read its state 15 s from the start of the read slot (see Figure 11). By the end of the read time slot, the DQ pin will pull back high via the external pullup resistor. All read time slots must be a minimum of 60 s in duration with a minimum of a 1- s recovery time between individual read slots.

Figure 12 shows that the sum of TINIT, TRC, and TSAMPLE must be less than 15 s. Figure 13 shows that system timing margin is maximized by keeping TINIT and TRC as small as possible and by locating the

master sample time towards the end of the 15- s period.

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DS18S20

READ/WRITE TIMING DIAGRAM Figure 11

VCC

1-WIRE

BUS

GND

VCC

1-WIRE

BUS

GND

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DS18S20

DETAILED MASTER READ 1 TIMING Figure 12

VCC

VIH OF MASTER

1-WIRE

BUS

GND

MASTER SAMPLES

15 s

RECOMMENDED MASTER READ 1 TIMING Figure 13

VCC

VIH OF MASTER

1-WIRE

BUS

GND

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