Материал: Разработка и прототипирование цифровых устройств на языках VHDL и Verilog. Барабанов В.Ф., Гребенникова Н.И
Код модели на языке VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dTrigger is
port(d:in std_logic; clk:in std_logic; reset:in std_logic; s:in std_logic; q:out std_logic;qn:out std_logic);
end entity;
architecture rtl of dTrigger is
begin
process (clk, reset, s) begin if (reset = '0') then
q <= '0'; qn <= '1';
elsif (s = '0') then q <= '1';
qn <= '0';
elsif (rising_edge(c)) then q <= d;
qn <= not d; end if;
end process; end architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity code_lab3 is
Port (clk : in STD_LOGIC; reset : in STD_LOGIC; res : out STD_LOGIC);
end code_lab3;
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architecture Behavioral of code_lab3 is
component dTrigger Port (d:in std_logic; clk:in std_logic; reset:in std_logic; s:in std_logic; q:out std_logic; qn:out std_logic);
end component ;
signal q1n: STD_LOGIC; signal q1: STD_LOGIC;
begin
c1: dTrigger port map( d => q1n,
clk => clk, reset => reset, s => '1',
q => q1,
qn => q1n ); c2: dTrigger port map(
d => q1, clk => clk,
reset => reset, s => '1',
q => res); end Behavioral;
Код тестовой оболочки на языке VHDL:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb2 IS
END tb2;
ARCHITECTURE behavior OF tb2 IS COMPONENT code_lab3
PORT(clk : IN std_logic; reset : IN std_logic; res : OUT std_logic);
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END COMPONENT;
signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal res : std_logic;
constant clk_period : time := 20 ns;
BEGIN
uut: code_lab3 PORT MAP (clk => clk, reset => reset, res => res);
clk_process :process begin
clk <= '0';
wait for clk_period/2; clk <= '1';
wait for clk_period/2; end process;
stim_proc: process begin
wait for clk_period*5;
reset <= '0'; wait for clk_period*2; reset <= '1';
wait;
end process; END;
Результат моделирования:
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ПРИЛОЖЕНИЕ 4
Пример выполнения задания лабораторной работы 4
Код модели автомата Мили на языке Verilog HDL
module mili(input c, data, reset, output reg [1:0] res);
reg [1:0] condition;
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3;
always @ (posedge c or posedge reset) begin if (reset)
state <= S0;
else
case (state) S0:
if (data) begin
condition <= s1;
end else begin
condition <= s1;
end
S1:
if (data) begin
condition <= s2;
end else begin
condition <= s1;
end
S2:
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if (data) begin
condition <= s3;
end else begin
condition <= s1;
end
S3:
if (data) begin
condition <= s2;
end else begin
condition <= s3;
end
endcase
end
always @ (condition or data) begin
case (state) s0:
if (data) begin
res = 2'b00;
end else begin
res = 2'b10;
end
s1:
if (data) begin
res = 2'b01;
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