Материал: AMBA_v30_AXI_v10
Channel Handshake
3-8
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
•
the slave can wait for
AWVALID
or
WVALID
, or both, before asserting
WREADY
•
the slave must wait for both
WVALID
and
WREADY
to be asserted before
asserting
BVALID
.
Figure 3-5 Write transaction handshake dependencies
Note
It is important that during a write transaction, a master must not wait for
AWREADY
to be asserted before driving
WVALID
. This could cause a deadlock condition if the
slave is conversely waiting for
WVALID
before asserting
AWREADY
.
WREADY
AWVALID
AWREADY
WVALID
BVALID
BREADY
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
4-1
Chapter 4
Addressing Options
This chapter describes AXI burst types and how to calculate addresses and byte lanes
for transfers within a burst. It contains the following sections:
•
•
•
•
•
Addressing Options
4-2
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
4.1
About addressing options
The AXI protocol is burst-based, and the master begins each burst by driving transfer
control information and the address of the first byte in the transfer. As the burst
transaction progresses, it is the responsibility of the slave to calculate the addresses of
subsequent transfers in the burst.
Bursts must not cross 4KB boundaries to prevent them from crossing boundaries
between slaves and to limit the size of the address incrementer required within slaves.
Addressing Options
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
4-3
4.2
Burst length
The
AWLEN
or
ARLEN
signal specifies the number of data transfers that occur within
each burst. As Table 4-1 shows, each burst can be 1-16 transfers long.
For wrapping bursts, the length of the burst must be 2, 4, 8, or 16 transfers.
Every transaction must have the number of transfers specified by
ARLEN
or
AWLEN
.
No component can terminate a burst early to reduce the number of data transfers.
During a write burst, the master can disable further writing by deasserting all the write
strobes, but it must complete the remaining transfers in the burst. During a read burst,
the master can discard further read data, but it must complete the remaining transfers in
the burst.
Caution
Discarding read data that is not required can result in lost data when accessing a
read-sensitive device such as a FIFO. A master must never access such a device using a
burst length longer than required.
Table 4-1 Burst length encoding
ARLEN[3:0]
AWLEN[3:0]
Number of
data transfers
b0000
1
b0001
2
b0010
3
.
.
.
b1101
14
b1110
15
b1111
16
Addressing Options
4-4
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
4.3
Burst size
Table 4-2 shows how the
ARSIZE
or
AWSIZE
signal specifies the maximum number
of data bytes to transfer in each beat, or data transfer, within a burst.
The AXI determines from the transfer address which byte lanes of the data bus to use
for each transfer.
For incrementing or wrapping bursts with transfer sizes narrower than the data bus, data
transfers are on different byte lanes for each beat of the burst. The address of a fixed
burst remains constant, and every transfer uses the same byte lanes.
The size of any transfer must not exceed the data bus width of the components in the
transaction.
Table 4-2 Burst size encoding
ARSIZE[2:0]
AWSIZE[2:0]
Bytes in
transfer
b000
1
b001
2
b010
4
b011
8
b100
16
b101
32
b110
64
b111
128