Материал: AMBA_v30_AXI_v10
Additional Control Information
5-2
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
5.1
Cache support
Support for system level caches and other performance enhancing components is
provided by the use of the cache information signals,
ARCACHE
and
AWCACHE
.
These signals provide additional information about how the transaction can be
processed.
The
ARCACHE[3:0]
or
AWCACHE[3:0]
signal supports system-level caches by
providing the bufferable, cacheable, and allocate attributes of the transaction:
Bufferable
(B) bit, ARCACHE[0] and AWCACHE[0]
When this bit is HIGH, it means that the interconnect or any component
can delay the transaction reaching its final destination for an arbitrary
number of cycles. This is usually only relevant to writes.
Cacheable
(C) bit, ARCACHE[1] and AWCACHE[1]
When this bit is HIGH, it means that the transaction at the final
destination does not have to match the characteristics of the original
transaction.
For writes this means that a number of different writes can be merged
together.
For reads this means that a location can be pre-fetched or can be fetched
just once for multiple read transactions.
To determine if a transaction should be cached this bit should be used in
conjunction with the
Read Allocate
(RA) and
Write Allocate
(WA) bits.
Read Allocate
(RA) bit, ARCACHE[2] and AWCACHE[2]
When the RA bit is HIGH, it means that if the transfer is a read and it
misses in the cache then it should be allocated.
The RA bit must not be HIGH if the C bit is low.
Write Allocate
(WA) bit, ARCACHE[3] and AWCACHE[3]
When the WA bit is HIGH, it means that if the transfer is a write and it
misses in the cache then it should be allocated.
The WA bit must not be HIGH if the C bit is low.
Additional Control Information
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
5-3
Table 5-1 shows the encoding of the
ARCACHE[3:0]
and
AWCACHE[3:0]
signals.
In the case of write transactions, the
AWCACHE
signal can be used to determine which
component provides the write response. If a write transaction is indicated as bufferable
then it is acceptable for a bridge or system level cache to provide the write response. If,
however, the transaction is indicated as being non-bufferable then the write response
must be provided from the final destination of the transaction.
Table 5-1 Cache encoding
ARCACHE[3:0]
AWCACHE[3:0]
Transaction attributes
WA
RA
C
B
0
0
0
0
Noncacheable and nonbufferable
0
0
0
1
Bufferable only
0
0
1
0
Cacheable, but do not allocate
0
0
1
1
Cacheable and bufferable, but do not allocate
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
Cacheable write-through, allocate on reads only
0
1
1
1
Cacheable write-back, allocate on reads only
1
0
0
0
Reserved
1
0
0
1
Reserved
1
0
1
0
Cacheable write-through, allocate on writes only
1
0
1
1
Cacheable write-back, allocate on writes only
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Cacheable write-through, allocate on both reads and writes
1
1
1
1
Cacheable write-back, allocate on both reads and writes
Additional Control Information
5-4
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
The AXI protocol does not determine the mechanism by which buffered or cached data
reaches its destination. For example, a system-level cache might have a controller to
manage cleaning, flushing, and invalidating cache entries. Another example is a bridge
containing a write buffer, which might have control logic to drain the buffer if it receives
a nonbufferable write with a matching transaction ID.
Additional Control Information
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
5-5
5.2
Protection unit support
To support complex system designs, it is often necessary for both the interconnect and
other devices in the system to provide protection against illegal transactions. The
AWPROT
or
ARPROT
signal gives three levels of access protection:
Normal or privileged, ARPROT[0] and AWPROT[0]
•
LOW indicates a normal access
•
HIGH indicates a privileged access.
This is used by some masters to indicate their processing mode. A
privileged processing mode typically has a greater level of access within
a system.
Secure or non-secure, ARPROT[1] and AWPROT[1]
•
LOW indicates a secure access
•
HIGH indicates a non-secure access.
This is used in systems where a greater degree of differentiation between
processing modes is required.
Note
This bit is configured so that when it is HIGH then the transaction is
considered non-secure and when LOW, the transaction is considered as
secure.
Instruction or data, ARPROT[2] and AWPROT[2]
•
LOW indicates a data access
•
HIGH indicates an instruction access.
This bit gives an indication if the transaction is an instruction or a data
access.
Note
This indication is provided as a hint and is not accurate in all cases. For
example, where a transaction contains a mix of instruction and data
items. It is recommended that, by default, an access is marked as a data
access unless it is specifically known to be an instruction access.
Additional Control Information
5-6
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
Table 5-2 summarizes the encoding of the
ARPROT[2:0]
and
AWPROT[2:0]
signals.
Table 5-2 Protection encoding
ARPROT[2:0]
AWPROT[2:0]
Protection level
[0]
1 = privileged access
0 = normal access
[1]
1 = nonsecure access
0 = secure access
[2]
1 = instruction access
0 = data access