Материал: AMBA_v30_AXI_v10
Channel Handshake
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
3-3
Figure 3-2 READY before VALID handshake
In Figure 3-3, both the source and destination happen to indicate in the same cycle that
they can transfer the data or control information. In this case the transfer occurs
immediately. The arrow shows when the transfer occurs.
Figure 3-3 VALID with READY handshake
The individual AXI protocol channel handshake mechanisms are described in:
•
•
•
•
•
3.1.1
Write address channel
The master can assert the
AWVALID
signal only when it drives valid address and
control information. It must remain asserted until the slave accepts the address and
control information and asserts the associated
AWREADY
signal.
The default value of
AWREADY
can be either HIGH or LOW. The recommended
default value is HIGH, although if
AWREADY
is HIGH then the slave must be able to
accept any valid address that is presented to it.
READY
VALID
INFORMATION
ACLK
READY
VALID
INFORMATION
ACLK
Channel Handshake
3-4
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
A default
AWREADY
value of LOW is possible but not recommended, because it
implies that the transfer takes at least two cycles, one to assert
AWVALID
and another
to assert
AWREADY
.
3.1.2
Write data channel
During a write burst, the master can assert the
WVALID
signal only when it drives valid
write data.
WVALID
must remain asserted until the slave accepts the write data and
asserts the
WREADY
signal.
The default value of
WREADY
can be HIGH, but only if the slave can always accept
write data in a single cycle.
The master must assert the
WLAST
signal when it drives the final write transfer in the
burst.
When
WVALID
is LOW, the
WSTRB[3:0]
signals can take any value, although it is
recommended that they are either driven LOW or held at their previous value.
3.1.3
Write response channel
The slave can assert the
BVALID
signal only when it drives a valid write response.
BVALID
must remain asserted until the master accepts the write response and asserts
BREADY
.
The default value of
BREADY
can be HIGH, but only if the master can always accept
a write response in a single cycle.
3.1.4
Read address channel
The master can assert the
ARVALID
signal only when it drives valid address and
control information. It must remain asserted until the slave accepts the address and
control information and asserts the associated
ARREADY
signal.
The default value of
ARREADY
can be either HIGH or LOW. The recommended
default value is HIGH, although if
ARREADY
is HIGH then the slave must be able to
accept any valid address that is presented to it.
A default
ARREADY
value of LOW is possible but not recommended, because it
implies that the transfer takes at least two cycles, one to assert
ARVALID
and another
to assert
ARREADY
.
Channel Handshake
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
3-5
3.1.5
Read data channel
The slave can assert the
RVALID
signal only when it drives valid read data.
RVALID
must remain asserted until the master accepts the data and asserts the
RREADY
signal.
Even if a slave has only one source of read data, it must assert the
RVALID
signal only
in response to a request for the data.
The master interface uses the
RREADY
signal to indicate that it accepts the data. The
default value of
RREADY
can be HIGH, but only if the master is able to accept read
data immediately, whenever it performs a read transaction.
The slave must assert the
RLAST
signal when it drives the final read transfer in the
burst.
Channel Handshake
3-6
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
3.2
Relationships between the channels
The relationship between the address, read, write, and write response channels is
flexible.
For example, the write data can appear at an interface before the write address that
relates to it. This can occur when the write address channel contains more register stages
than the write data channel. It is also possible for the write data to appear in the same
cycle as the address.
When the interconnect must determine the destination address space or slave space, it
must realign the address and write data. This is required to assure that the write data is
signaled as valid only to the slave for which it is destined.
Two relationships that must be maintained are:
•
read data must always follow the address to which the data relates
•
a write response must always follow the last write transfer in the write transaction
to which the write response relates.
Channel Handshake
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
3-7
3.3
Dependencies between channel handshake signals
To prevent a deadlock situation, you must observe the dependencies that exist between
the handshake signals.
In any transaction:
•
the
VALID
signal of one AXI component must not be dependent on the
READY
signal of the other component in the transaction
•
the
READY
signal can wait for assertion of the
VALID
signal.
Note
While it is acceptable to wait for
VALID
to be asserted before asserting
READY
, it is
also acceptable to assert
READY
by default prior to the assertion of
VALID
and this
can result in a more efficient design.
Figure 3-4 and Figure 3-5 on page 3-8 show the handshake signal dependencies. The
single-headed arrows point to signals that can be asserted before or after the previous
signal is asserted. Double-headed arrows point to signals that must be asserted only after
assertion of the previous signal.
Figure 3-4 shows that, in a read transaction:
•
the slave can wait for
ARVALID
to be asserted before it asserts
ARREADY
•
the slave must wait for both
ARVALID
and
ARREADY
to be asserted before it
starts to return read data by asserting
RVALID
.
Figure 3-4 Read transaction handshake dependencies
Figure 3-5 on page 3-8 shows that, in a write transaction:
•
the master must not wait for the slave to assert
AWREADY
or
WREADY
before
asserting
AWVALID
or
WVALID
•
the slave can wait for
AWVALID
or
WVALID
, or both, before asserting
AWREADY
ARVALID
ARREADY
RVALID
RREADY