Материал: AMBA_v30_AXI_v10
Addressing Options
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
4-5
4.4
Burst type
The AXI protocol defines three burst types described in:
•
•
•
Table 4-3 shows how the
ARBURST
or
AWBURST
signal selects the burst type.
4.4.1
Fixed burst
In a fixed burst, the address remains the same for every transfer in the burst. This burst
type is for repeated accesses to the same location such as when loading or emptying a
peripheral FIFO.
4.4.2
Incrementing burst
In an incrementing burst, the address for each transfer in the burst is an increment of the
previous transfer address. The increment value depends on the size of the transfer. For
example, the address for each transfer in a burst with a size of four bytes is the previous
address plus four.
Table 4-3 Burst type encoding
ARBURST[1:0]
AWBURST[1:0]
Burst type
Description
Access
b00
FIXED
Fixed-address burst
FIFO-type
b01
INCR
Incrementing-address burst
Normal sequential memory
b10
WRAP
Incrementing-address burst that wraps
to a lower address at the wrap boundary
Cache line
b11
Reserved
-
-
Addressing Options
4-6
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
4.4.3
Wrapping burst
A wrapping burst is similar to an incrementing burst, in that the address for each transfer
in the burst is an increment of the previous transfer address. However, in a wrapping
burst the address wraps around to a lower address when a wrap boundary is reached.
The wrap boundary is the size of each transfer in the burst multiplied by the total
number of transfers in the burst.
Two restrictions apply to wrapping bursts:
•
the start address must be aligned to the size of the transfer
•
the length of the burst must be 2, 4, 8, or 16.
Addressing Options
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
4-7
4.5
Burst address
This section provides some simple formulas for determining the address and byte lanes
of transfers within a burst. The formulas use the following variables:
Start_Address
The start address issued by the master.
Number_Bytes
The maximum number of bytes in each data transfer.
Data_Bus_Bytes
The number of byte lanes in the data bus.
Aligned_Address
The aligned version of the start address.
Burst_Length
The total number of data transfers within a burst.
Address_N
The address of transfer N within a burst. N is an integer from 2-16.
Wrap_Boundary
The lowest address within a wrapping burst.
Lower_Byte_Lane
The byte lane of the lowest addressed byte of a transfer.
Upper_Byte_Lane
The byte lane of the highest addressed byte of a transfer.
INT(x)
The rounded-down integer value of x.
Use these equations to determine addresses of transfers within a burst:
•
Start_Address
=
ADDR
•
Number_Bytes
= 2
SIZE
•
Burst_Length
=
LEN
+ 1
•
Aligned_Address
= (INT(
Start_Address
/
Number_Bytes
) ) x
Number_Bytes
.
Use this equation to determine the address of the first transfer in a burst:
•
Address_1
=
Start_Address
.
Use this equation to determine the address of any transfer after the first transfer in a
burst:
•
Address_N
=
Aligned_Address
+ (N – 1) x
Number_Bytes
.
For wrapping bursts, the
Wrap_Boundary
variable is extended to account for the wrapping
boundary:
•
Wrap_Boundary
= (
INT
(
Start_Address
/ (
Number_Bytes
x
Burst_Length
)))
x (
Number_Bytes
x
Burst_Length
).
If
Address_N
=
Wrap_Boundary
+ (
Number_Bytes
x
Burst_Length
), use this equation:
•
Address_N
=
Wrap_Boundary
.
Addressing Options
4-8
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
Use these equations to determine which byte lanes to use for the first transfer in a burst:
•
Lower_Byte_Lane
=
Start_Address
- (
INT
(
Start_Address
/
Data_Bus_Bytes
))
x
Data_Bus_Bytes
•
Upper_Byte_Lane
=
Aligned_Address
+ (
Number_Bytes
- 1) -
(
INT
(
Start_Address
/
Data_Bus_Bytes
)) x
Data_Bus_Bytes
.
Use these equations to determine which byte lanes to use for all transfers after the first
transfer in a burst:
•
Lower_Byte_Lane
=
Address_N
– (
INT
(
Address_N
/
Data_Bus_Bytes
))
x
Data_Bus_Bytes
•
Upper_Byte_Lane
=
Lower_Byte_Lane
+
Number_Bytes
– 1.
Data is transferred on:
•
DATA[(8 x
Upper_Byte_Lane
) + 7 : (8 x
Lower_Byte_Lane
)].
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
5-1
Chapter 5
Additional Control Information
This chapter describes AXI protocol support for system-level caches and protection
units. It contains the following sections:
•
•