Материал: AMBA_v30_AXI_v10
Atomic Accesses
6-6
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
6.2.5
Slaves that do not support exclusive access
The response signals,
BRESP[1:0]
and
RRESP[1:0]
, include an OKAY response for
successful normal accesses and an EXOKAY response for successful exclusive
accesses. This means that a slave that does not support exclusive accesses can provide
an OKAY response to indicate the failure of an exclusive access.
Note
An exclusive write to a slave that does not support exclusive access always updates the
memory location.
An exclusive write to a slave that supports exclusive access updates the memory
location only if the exclusive write is successful.
Atomic Accesses
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
6-7
6.3
Locked access
When the
ARLOCK[1:0]
or
AWLOCK[1:0]
signals for a transaction show that it is a
locked transfer then the interconnect must ensure that only that master is allowed access
to the slave region until an unlocked transfer from the same master completes. The
arbiter within the interconnect is used to enforce this restriction.
When a master starts a locked sequence of either read or write transactions it must
ensure that it has no other outstanding transactions waiting to complete.
Any transaction with
ARLOCK[1:0]
or
AWLOCK[1:0]
set to indicate a locked
sequence forces the interconnect to lock the following transaction. Therefore, a locked
sequence must always complete with a final transaction that does not have
ARLOCK[1:0]
or
AWLOCK[1:0]
set to indicate a locked access. This final
transaction is included in the locked sequence and effectively removes the lock.
When completing a locked sequence a master must ensure that all previous locked
transactions are complete before issuing the final unlocking transaction. It must then
ensure that the final unlocking transaction has fully completed before any further
transactions are commenced.
The master must ensure that all transactions within a locked sequence have the same
ARID
or
AWID
value.
Note
Locked accesses require that the interconnect prevents any other transactions occurring
while the locked sequence is in progress and can therefore have an impact on the
interconnect performance. It is recommended that locked accesses are only used to
support legacy devices.
The following restrictions are recommended but not mandatory:
•
keep all locked transaction sequences within the same 4KB address region
•
limit locked transaction sequences to two transactions.
Atomic Accesses
6-8
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
7-1
Chapter 7
Response Signaling
This chapter describes the four slave responses in AXI read and write transactions. It
contains the following sections:
•
•
Response Signaling
7-2
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
7.1
About response signaling
The AXI protocol allows response signalling for both read and write transactions. For
read transactions the response information from the slave is passed alongside the read
data itself, however for writes the response information is conveyed along the write
response channel.
The AXI protocol responses are:
•
OKAY
•
EXOKAY
•
SLVERR
•
DECERR.
Table 7-1 shows the encoding of the
RRESP[1:0]
and
BRESP[1:0]
signals.
For a write transaction, there is just one response given for the entire burst and not for
each data transfer within the burst.
In a read transaction, the slave can give different responses for different transfers within
a burst. In a burst of 16 read transfers, for example, the slave might return an OKAY
response for 15 of the transfers and a SLVERR response for one of the transfers.
The protocol defines that the required number of data transfers must be performed, even
if an error is reported. For example, if a read of 8 transfers is requested from a slave but
the slave has an error condition then the slave must perform 8 data transfers, each with
an error response. The remainder of the burst is not cancelled if the slave gives a single
error response.
Table 7-1 RRESP[1:0] and BRESP[1:0] encoding
RRESP[1:0]
BRESP[1:0]
Response
Meaning
b00
OKAY
Normal access okay indicates if a normal access has been successful. Can also indicate
an exclusive access failure.
b01
EXOKAY
Exclusive access okay indicates that either the read or write portion of an exclusive access
has been successful.
b10
SLVERR
Slave error is used when the access has reached the slave successfully, but the slave
wishes to return an error condition to the originating master.
b11
DECERR
Decode error is generated typically by an interconnect component to indicate that there
is no slave at the transaction address.