Материал: AMBA_v30_AXI_v10

ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

xi

List of Figures

AMBA AXI Protocol Specification

Key to timing diagram conventions  ............................................................................ xvi

Figure 1-1

Channel architecture of reads  ...................................................................................  1-3

Figure 1-2

Channel architecture of writes ...................................................................................  1-4

Figure 1-3

Interface and interconnect .........................................................................................  1-5

Figure 1-4

Read burst .................................................................................................................  1-7

Figure 1-5

Overlapping read bursts  ............................................................................................  1-8

Figure 1-6

Write burst  .................................................................................................................  1-9

Figure 3-1

VALID before READY handshake .............................................................................  3-2

Figure 3-2

READY before VALID handshake .............................................................................  3-3

Figure 3-3

VALID with READY handshake  ................................................................................  3-3

Figure 3-4

Read transaction handshake dependencies  .............................................................  3-7

Figure 3-5

Write transaction handshake dependencies  .............................................................  3-8

Figure 9-1

Byte lane mapping  ....................................................................................................  9-3

Figure 9-2

Narrow transfer example with 8-bit transfers .............................................................  9-4

Figure 9-3

Narrow transfer example with 32-bit transfers ...........................................................  9-4

Figure 9-4

Example mixed-endian data structure .......................................................................  9-5

Figure 10-1

Aligned and unaligned word transfers on a 32-bit bus  ............................................  10-3

Figure 10-2

Aligned and unaligned word transfers on a 64-bit bus  ............................................  10-4

Figure 10-3

Aligned wrapping word transfers on a 64-bit bus  ....................................................  10-4

Figure 11-1

Exit from reset  .........................................................................................................  11-2

Figure 12-1

CSYSREQ and CSYSACK handshake  ...................................................................  12-3

Figure 12-2

Acceptance of a low-power request  ........................................................................  12-4

Figure 12-3

Denial of a low-power request .................................................................................  12-5

Figure 12-4

Low-power clock control sequence  .........................................................................  12-6

xii

Copyright © 2003, 2004 ARM Limited. All rights reserved.

ARM IHI 0022B

ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

xiii

Preface

This preface introduces the 

AMBA Advanced eXtensible Interface (AXI) Protocol 

Specification

 and its reference documentation. It contains the following sections:

•

About this document

 on page xiv

•

Feedback

 on page xviii.

Preface 

xiv

Copyright © 2003, 2004 ARM Limited. All rights reserved.

ARM IHI 0022B

About this document

This is the AMBA AXI Protocol Specification v1.0. This issue supersedes the previous 
r0p0 version of the specification.

Intended audience

This specification is written to help hardware and software engineers who want to 
become familiar with the 

Advanced Microcontroller Bus Architecture

 (AMBA) and 

design systems and modules that are compatible with the AXI protocol.

Using this specification

This specification is organized into the following chapters:

Chapter 1 

Introduction

Read this chapter to learn about the AXI protocol architecture and the 
basic transactions that it defines.

Chapter 2 

Signal Descriptions

Refer to this chapter for definitions of the AXI global, write address 
channel, write data channel, write response channel, read address 
channel, read data channel, and low-power interface signals.

Chapter 3 

Channel Handshake

Read this chapter to learn about the AXI channel handshake process.

Chapter 4 

Addressing Options

Read this chapter to learn about AXI burst types and how to calculate 
addresses and byte lanes for transfers within a burst.

Chapter 5 

Additional Control Information

Read this chapter to learn how to use the AXI protocol to support system 
level caches and protection units.

Chapter 6 

Atomic Accesses

Read this chapter to learn how to perform exclusive accesses and locked 
accesses.

Chapter 7 

Response Signaling

Read this chapter to learn about the four transaction responses of AXI 
slaves.

Preface 

ARM IHI 0022B

Copyright © 2003, 2004 ARM Limited. All rights reserved.

xv

Chapter 8 

Ordering Model

Read this chapter to learn how the AXI protocol uses transaction ID tags 
to enable out-of-order transaction processing.

Chapter 9 

Data Buses

Read this chapter to learn how to do transactions of varying sizes on the 
AXI read and write data buses and how to use byte-invariant endianness 
to handle mixed-endian data.

Chapter 10 

Unaligned Transfers

Read this chapter to learn how the AXI protocol handles unaligned 
transfers.

Chapter 11 

Clock and Reset

Read this chapter to learn about the timing of the AXI clock and reset 
signals.

Chapter 12 

Low-power Interface

Read this chapter to learn how to use the AXI clock control interface to 
enter into and exit from a low-power state.

Conventions

Conventions that this specification can use are described in:

•

Typographical

•

Timing diagrams

 on page xvi

•

Signals

 on page xvii.

Typographical

The typographical conventions are:

italic

Highlights important notes, introduces special terminology, 
denotes internal cross-references, and citations.

bold  

Highlights interface elements, such as menu names. Denotes 
ARM signal names. Also used for terms in descriptive lists, where 
appropriate.

monospace

Denotes text that you can enter at the keyboard, such as 
commands, file and program names, and source code.