Материал: AMBA_v30_AXI_v10
Preface
xvi
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
monospace
Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.
monospace
italic
Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace
bold
Denotes language keywords when used outside example code.
< and >
Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
•
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
•
The Opcode_2 value selects which register is accessed.
Timing diagrams
Key to timing diagram conventions
explains the components used in
timing diagrams. Variations, when they occur, have clear labels. You must not assume
any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Key to timing diagram conventions
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Preface
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
xvii
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means HIGH for
active-HIGH signals and LOW for active-LOW signals.
Prefix A
Denotes AXI global, write address, and read address channel
signals.
Prefix B
Denotes AXI write response channel signals.
Prefix C
Denotes AXI low-power interface signals.
Prefix R
Denotes AXI read data channel signals.
Prefix W
Denotes AXI write data channel signals.
Suffix n
Denotes that the AXI
ARESETn
global reset signal is
active-LOW.
Further reading
This section lists publications by ARM Limited.
ARM periodically provides updates and corrections to its documentation. See
http://www.arm.com
and
http://www.amba.com
for current errata sheets, addenda, and the
ARM and AMBA Frequently Asked Questions list.
ARM publications
This specification contains information that is specific to the AXI protocol. Refer to the
following documents for other relevant information:
•
AMBA Specification (Rev 2.0)
(ARM IHI 0011)
•
ARM Architecture Reference Manual
(ARM DDI 0100).
Preface
xviii
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
Feedback
ARM Limited welcomes feedback on the AMBA AXI protocol and its documentation.
Feedback on this product
If you have any comments or suggestions about this product, contact your supplier
giving:
•
the product name
•
a concise explanation of your comments.
Feedback on this specification
If you have any comments on this specification, send email to
errata@arm.com
giving:
•
the title
•
the number
•
the relevant page number(s) to which your comments apply
•
a concise explanation of your comments.
ARM Limited also welcomes general suggestions for additions and improvements.
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
1-1
Chapter 1
Introduction
This chapter describes the architecture of the AXI protocol and the basic transactions
that the protocol defines. It contains the following sections:
•
•
•
•
Introduction
1-2
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
1.1
About the AXI protocol
The AMBA AXI protocol is targeted at high-performance, high-frequency system
designs and includes a number of features that make it suitable for a high-speed
submicron interconnect.
The objectives of the latest generation AMBA interface are to:
•
be suitable for high-bandwidth and low-latency designs
•
enable high-frequency operation without using complex bridges
•
meet the interface requirements of a wide range of components
•
be suitable for memory controllers with high initial access latency
•
provide flexibility in the implementation of interconnect architectures
•
be backward-compatible with existing AHB and APB interfaces.
The key features of the AXI protocol are:
•
separate address/control and data phases
•
support for unaligned data transfers using byte strobes
•
burst-based transactions with only start address issued
•
separate read and write data channels to enable low-cost
Direct Memory Access
(DMA)
•
ability to issue multiple outstanding addresses
•
out-of-order transaction completion
•
easy addition of register stages to provide timing closure.
As well as the data transfer protocol, the AXI protocol includes optional extensions that
cover signaling for low-power operation.