Материал: AMBA_v30_AXI_v10
Response Signaling
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
7-3
This protocol places restrictions on masters that can issue multiple outstanding
addresses and that must also support precise error signaling. Such masters must be able
to handle an error response for an earlier transfer while later transfers are already
underway.
Response Signaling
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Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
7.2
Response types
This section describes the four AXI protocol response types:
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7.2.1
Normal access success
The OKAY response indicates:
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the success of a normal access
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the failure of an exclusive access
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an exclusive access to a slave that does not support exclusive access.
OKAY is the response for most transactions.
7.2.2
Exclusive access
The EXOKAY response indicates the success of an exclusive access. Chapter 6
describes this response.
7.2.3
Slave error
The SLVERR response indicates an unsuccessful transaction. Examples of slave error
conditions are:
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FIFO/buffer overrun or underrun condition
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unsupported transfer size attempted
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write access attempted to read-only location
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timeout condition in the slave
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access attempted to an address where no registers are present
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access attempted to a disabled or powered-down function.
To simplify system monitoring and debugging, it is recommended that error responses
are used only for error conditions and not for signaling normal, expected events.
7.2.4
Decode error
In a system without a fully-decoded address map, there can be addresses at which there
are no slaves to respond to a transaction. In such a system, the interconnect must provide
a suitable error response to flag the access as illegal and also to prevent the system from
locking up by trying to access a nonexistent slave.
Response Signaling
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
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When the interconnect cannot successfully decode a slave access, it effectively routes
the access to a default slave, and the default slave returns the DECERR response.
An implementation option is to have the default slave also record the details of decode
errors for later determination of how the errors occurred. In this way, the default slave
can significantly simplify the debugging process.
The AXI protocol requires that all data transfers for a transaction are completed, even
if an error condition occurs. Therefore any component giving a DECERR response must
meet this requirement.
Response Signaling
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Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
8-1
Chapter 8
Ordering Model
This chapter describes how the AXI protocol uses transaction ID tags to enable the
issuing of multiple outstanding addresses and out-of-order transaction processing. It
contains the following sections:
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