Материал: AMBA_v30_AXI_v10
Ordering Model
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
8-7
To avoid a deadlock situation, a slave interface must have a write interleaving depth
greater than one only if it can continuously accept interleaved write data. The slave
interface must never stall the acceptance of write data in an attempt to change the order
of the write data.
Ordering Model
8-8
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
8.6
Read and write interaction
There are no ordering restrictions between read and write transactions and they are
allowed to complete in any order.
If a master requires a given relationship between read and write transaction then it must
ensure that the earlier transaction is complete before issuing the later transaction. In the
case of reads the earlier transaction can be considered complete when the last read data
is returned to the master. In the case of writes the transaction can only be considered
complete when the write response is received by the master, it is not acceptable to
consider the write transaction complete when all the write data is sent.
For address regions occupied by peripherals this typically means waiting for earlier
transactions to complete when switching between read and write transactions that
require an ordering restriction.
For memory regions, it is possible for a master to implement an address check against
outstanding transactions, to determine if a new transaction could be to the same, or
overlapping, address region. If the transactions do not overlap then the new transaction
can commence without waiting for earlier transactions to complete.
Ordering Model
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
8-9
8.7
Interconnect use of ID fields
When a master interface is connected to an interconnect, the interconnect appends
additional bits to the
ARID
,
AWID
and
WID
fields that are unique to that master port.
This has two effects:
•
masters do not have to know what ID values are used by other masters, because
the interconnect makes the ID values unique when it appends the master number
to the field
•
the width of the ID field at a slave interface is wider than the ID field at a master
interface.
For read data, the interconnect uses the additional bits of the
RID
field to determine
which master port the read data is destined for. The interconnect removes these bits of
the
RID
field before passing the
RID
value to the correct master port.
Ordering Model
8-10
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
8.8
Recommended width of ID fields
To take advantage of the AXI out-of-order transaction capability, use the following
recommendations:
•
implement a transaction ID up to four bits in master components
•
implement up to four additional bits of transaction ID for master port numbers in
the interconnect
•
implement eight bits of ID support in slave components.
Note
For masters that support only a single ordered interface, it is acceptable to tie the ID
outputs to a constant value, such as 0.
For slaves which do not make use of the ordering information and simply process all
transactions in order, it is possible to use a standard off-the-shelf module to add the ID
functionality to the slave, therefore making it possible to design the base functionality
of the slave without the ID signaling present.
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
9-1
Chapter 9
Data Buses
This chapter describes transfers of varying sizes on the AXI read and write data buses
and how the interface uses byte-invariant endianness to handle mixed-endian transfers.
It contains the following sections:
•
•
•
•