Материал: AMBA_v30_AXI_v10
Introduction
1-8
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
1.3.2
Overlapping read burst example
Figure 1-5 shows how a master can drive another burst address after the slave accepts
the first address. This enables a slave to begin processing data for the second burst in
parallel with the completion of the first burst.
Figure 1-5 Overlapping read bursts
ARADDR
A
T12
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
ARVALID
ARREADY
B
D(A0)
D(A1)
D(A2)
D(B0)
D(B1)
RVALID
RDATA
RLAST
RREADY
ACLK
Introduction
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Copyright © 2003, 2004 ARM Limited. All rights reserved.
1-9
1.3.3
Write burst example
Figure 1-6 shows a write transaction. The process starts when the master sends an
address and control information on the write address channel. The master then sends
each item of write data over the write data channel. When the master sends the last data
item, the
WLAST
signal goes HIGH. When the slave has accepted all the data items, it
drives a write response back to the master to indicate that the write transaction is
complete.
Figure 1-6 Write burst
1.3.4
Transaction ordering
The AXI protocol enables out-of-order transaction completion. It gives an ID tag to
every transaction across the interface. The protocol requires that transactions with the
same ID tag are completed in order, but transactions with different ID tags can be
completed out of order.
Out-of-order transactions can improve system performance in two ways:
•
The interconnect can enable transactions with fast-responding slaves to complete
in advance of earlier transactions with slower slaves.
AWADDR
A
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
AWVALID
AWREADY
D(A0)
WVALID
WDATA
WLAST
WREADY
BVALID
BRESP
BREADY
ACLK
D(A1)
D(A2)
D(A3)
OKAY
Introduction
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Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
•
Complex slaves can return read data out of order. For example, a data item for a
later access might be available from an internal buffer before the data for an
earlier access is available.
If a master requires that transactions are completed in the same order that they are
issued, then they must all have the same ID tag. If, however, a master does not require
in-order transaction completion, it can supply the transactions with different ID tags,
enabling them to be completed in any order.
In a multimaster system, the interconnect is responsible for appending additional
information to the ID tag to ensure that ID tags from all masters are unique. The ID tag
is similar to a master number, but with the extension that each master can implement
multiple virtual masters within the same port by supplying an ID tag to indicate the
virtual master number.
Although complex devices can make use of the out-of-order facility, simple devices are
not required to use it. Simple masters can issue every transaction with the same ID tag,
and simple slaves can respond to every transaction in order, irrespective of the ID tag.
Introduction
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Copyright © 2003, 2004 ARM Limited. All rights reserved.
1-11
1.4
Additional features
The AXI protocol also supports the following additional features:
Burst types
The AXI protocol supports three different burst types that are suitable for:
•
normal memory accesses
•
wrapping cache line bursts
•
streaming data to peripheral FIFO locations.
.
System cache support
The cache-support signal of the AXI protocol enables a master to provide
to a system-level cache the bufferable, cacheable, and allocate attributes
of a transaction.
Protection unit support
To enable both privileged and secure accesses, the AXI protocol provides
three levels of protection unit support.
Atomic operations
The AXI protocol defines mechanisms for both exclusive and locked
accesses.
.
Error support
The AXI protocol provides error support for both address decode errors
and slave-generated errors.
.
Unaligned address
To enhance the performance of the initial accesses within a burst, the AXI
protocol supports unaligned burst start addresses.
Introduction
1-12
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B