Материал: AMBA_v30_AXI_v10
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
2-1
Chapter 2
Signal Descriptions
This chapter defines the AXI signals. Although bus width and transaction ID width are
implementation-specific, the tables in this chapter show a 32-bit data bus, a four-bit
write data strobe, and four-bit ID fields. This chapter contains the following sections:
•
•
•
•
Write response channel signals
•
•
•
Signal Descriptions
2-2
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
2.1
Global signals
Table 2-1 lists the global AXI signals.
Table 2-1 Global signals
Signal
Source
Description
ACLK
Clock source
Global clock signal. All signals are sampled on the rising edge of the global clock.
ARESETn
Reset source
Global reset signal. This signal is active LOW.
Signal Descriptions
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
2-3
2.2
Write address channel signals
Table 2-2 lists the AXI write address channel signals.
Table 2-2 Write address channel signals
Signal
Source
Description
AWID[3:0]
Master
Write address ID. This signal is the identification tag for the write address group of
signals.
AWADDR[31:0]
Master
Write address. The write address bus gives the address of the first transfer in a write burst
transaction. The associated control signals are used to determine the addresses of the
remaining transfers in the burst.
AWLEN[3:0]
Master
Burst length. The burst length gives the exact number of transfers in a burst. This
information determines the number of data transfers associated with the address. See
Table 4-1 on page 4-3.
AWSIZE[2:0]
Master
Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes
indicate exactly which byte lanes to update. See Table 4-2 on page 4-4.
AWBURST[1:0]
Master
Burst type. The burst type, coupled with the size information, details how the address for
each transfer within the burst is calculated. See Table 4-3 on page 4-5.
AWLOCK[1:0]
Master
Lock type. This signal provides additional information about the atomic characteristics
of the transfer. See Table 6-1 on page 6-2.
AWCACHE[3:0]
Master
Cache type. This signal indicates the bufferable, cacheable, write-through, write-back,
and allocate attributes of the transaction. See Table 5-1 on page 5-3.
AWPROT[2:0]
Master
Protection type. This signal indicates the normal, privileged, or secure protection level
of the transaction and whether the transaction is a data access or an instruction access.
See
AWVALID
Master
Write address valid. This signal indicates that valid write address and control
information are available:
1 = address and control information available
0 = address and control information not available.
The address and control information remain stable until the address acknowledge signal,
AWREADY
, goes HIGH.
AWREADY
Slave
Write address ready. This signal indicates that the slave is ready to accept an address and
associated control signals:
1 = slave ready
0 = slave not ready.
Signal Descriptions
2-4
Copyright © 2003, 2004 ARM Limited. All rights reserved.
ARM IHI 0022B
2.3
Write data channel signals
Table 2-3 lists the AXI write data channel signals.
Table 2-3 Write data channel signals
Signal
Source
Description
WID[3:0]
Master
Write ID tag. This signal is the ID tag of the write data transfer. The
WID
value must match
the
AWID
value of the write transaction.
WDATA[31:0]
Master
Write data. The write data bus can be 8, 16, 32, 64, 128, 256, 512, or 1024 bits wide.
WSTRB[3:0]
Master
Write strobes. This signal indicates which byte lanes to update in memory. There is one
write strobe for each eight bits of the write data bus. Therefore,
WSTRB[n]
corresponds
to
WDATA[(8
×
n) + 7:(8
×
n)]
.
WLAST
Master
Write last. This signal indicates the last transfer in a write burst.
WVALID
Master
Write valid. This signal indicates that valid write data and strobes are available:
1 = write data and strobes available
0 = write data and strobes not available.
WREADY
Slave
Write ready. This signal indicates that the slave can accept the write data:
1 = slave ready
0 = slave not ready.
Signal Descriptions
ARM IHI 0022B
Copyright © 2003, 2004 ARM Limited. All rights reserved.
2-5
2.4
Write response channel signals
Table 2-4 lists the AXI write response channel signals.
Table 2-4 Write response channel signals
Signal
Source
Description
BID[3:0]
Slave
Response ID. The identification tag of the write response. The
BID
value must match the
AWID
value of the write transaction to which the slave is responding.
BRESP[1:0]
Slave
Write response. This signal indicates the status of the write transaction. The allowable
responses are OKAY, EXOKAY, SLVERR, and DECERR.
BVALID
Slave
Write response valid. This signal indicates that a valid write response is available:
1 = write response available
0 = write response not available.
BREADY
Master
Response ready. This signal indicates that the master can accept the response information.
1 = master ready
0 = master not ready.